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| switi switching ic pef 20451 htsi pef 20471 htsi-l pef 24471 htsi-xl version 1.3 preliminary data sheet, ds 1, nov. 2001 wired communications never stop thinking.
edition 2001-11-16 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2001. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. wired communications p r e l i m i n a r y switi switching ic pef 20451 htsi pef 20471 htsi-l pef 24471 htsi-xl version 1.3 preliminary data sheet, ds 1, nov. 2001 never stop thinking. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com pef 20451 / 20471 / 24471 preliminary revision history: 2001-11-16 ds 1 previous version: pef 20451 / 20471 / 24471 v1.2, preliminary data sheet ds1, 2001-04-04 page content 20 table 6 updated 35 chapter 3.4.4 updated, added figure 14 43 chapter 3.7.1 and chapter 3.7.2 updated 49 chapter 4.3 reworked 68 description of configuration command register 1 and 2 ( cmd1 and cmd2 ) updated 78 description of interrupt status register 1 ( ista1 ) reworked 79 description of interrupt error status register 1 and 2 ( iesta1 and iesta2 ) reworked 83 description of interrupt error mask register ( intem2 ) reworked 91 description of source address ( sa ) and destination address ( da ) registers updated 97 chapter 6.2 reworked 112 chapter 6.8.3 reworked 128 chapter 7.1 and table 27 ?pcm timing? updated 131 table 28 ?pcm parallel mode timing? 144 table 35 and figure 57 updated 146 added chapter 7.8, ?hardware reset timing? pef 20451 / 20471 / 24471 preliminary data sheet 2001-11-16 table of contents page 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 overview of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 features in detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4.1 standard pbx or co application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4.2 computer telephony application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4.3 router / remote access application . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4.4 voice over ip application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.1 h-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.2 local bus interface (pcm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.3 general purpose port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.4 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.5 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.6 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.7 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 architectural description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 overview of functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 switching factory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.1 switching modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.1.1 minimum and constant delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.1.2 subchannel switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.1.3 multipoint switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.1.4 broadcast switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.1.5 bidirectional switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.1.6 stream-to-stream switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.1.7 message mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.2 parallel mode for local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.3 switching block error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3.4 analyze connection and data memory . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4 clock generator and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.1 general overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.2 analog pll (apll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.4.2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4.2.2 jitter-transfer-function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4.3 master-slave selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.4.4 phase alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.4.5 pll synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 pef 20451 / 20471 / 24471 preliminary data sheet 2001-11-16 table of contents page 3.4.5.1 pll synchronization h-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.4.5.2 pll synchronization m-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.4.6 pll error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.4.7 clock fallback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.4.7.1 clock signal monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.4.7.2 clock fallback mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.5 loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.6 read switi configuration with indirect register addressing . . . . . . . . . . 42 3.7 power-on and reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.7.1 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.7.2 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4 description of interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.1 local bus interface (pcm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.2 h-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.2.1 ct_c8(a/b) and ct_frame(a/b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2.2 dataports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2.3 c t_en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.2.4 ct_reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.2.5 h-mvip c16 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.3 data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.4.1 intel/siemens or motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.4.2 de-multiplexed or multiplexed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.5 general purpose port (gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.6 general purpose clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6.1 frame group outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6.2 gpclk as clock outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.7 jtag (boundary scan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.7.1 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.7.2 test-access-port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.7.3 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.8 identification code via p read access . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.1 register overview for 8-bit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.2 detailed register description for 8-bit interface . . . . . . . . . . . . . . . . . . . . 61 5.3 register overview for 16-bit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.4 detailed register description for 16-bit interface . . . . . . . . . . . . . . . . . . 91 6 programming the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.1 read and write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.2 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.3 command and register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 pef 20451 / 20471 / 24471 preliminary data sheet 2001-11-16 table of contents page 6.4 indirect configuration register access . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.5 initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.6 h.1x0 clocking unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.7 pcm clocking unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.8 h.1x0/pcm line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.8.1 standby command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.8.2 determining clock rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.8.3 performing bit shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.8.3.1 input bit shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.8.3.2 output bit shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.9 global clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.9.1 framing groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.10 read time-slot value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.11 establish connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.11.1 establish 8-bit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.11.2 subchannel switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.11.2.1 establish 4-bit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.11.2.2 establish 2-bit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.11.2.3 establish 1-bit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.11.3 establish broadcast connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.11.4 establish subchannel broadcast connection . . . . . . . . . . . . . . . . . . . 121 6.11.5 establish multipoint connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.12 send messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.13 release connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.13.1 release 8-bit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.13.2 release 4-bit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.13.3 release 2-bit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.13.4 release 1-bit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 6.13.5 release broadcast connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.13.6 release subchannel broadcast connection . . . . . . . . . . . . . . . . . . . . 126 6.13.7 release multipoint connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.14 stop sending messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 7 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.1 pcm interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.2 pcm parallel mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7.3 h-bus and pcm (local bus) frame structure . . . . . . . . . . . . . . . . . . . . . 132 7.4 h-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 7.5 clock interoperability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 7.6 microprocessor interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 7.6.1 infineon/intel timing in de-multiplexed mode . . . . . . . . . . . . . . . . . . . 138 7.6.2 infineon/intel timing in multiplexed mode . . . . . . . . . . . . . . . . . . . . . . 139 7.6.3 motorola microprocessor timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 pef 20451 / 20471 / 24471 preliminary data sheet 2001-11-16 table of contents page 7.7 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.8 hardware reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.3 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 8.4 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 8.5 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 8.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 pef 20451 / 20471 / 24471 preliminary data sheet 2001-11-16 list of figures page figure 1 logic symbol: htsi in h-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2 logic symbol: htsi in m-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3 standard pbx or co application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4 ct application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5 router / remote access applications . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6 voice over ip application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9 bidirectional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10 example for stream-to-stream switching . . . . . . . . . . . . . . . . . . . . . . 29 figure 11 switi clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 12 block diagram of apll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 13 apll - jitter transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 14 example of phase alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 15 clock fallback of primary master . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 16 clock fallback of secondary master . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 17 clock fallback of slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 18 pcm interface configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 19 pcm bit shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 20 h-bus interface in h.100 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 21 h-bus interface in h.110 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 22 multiplexed and in de-multiplexed bus mode . . . . . . . . . . . . . . . . . . . 51 figure 23 gpio port configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 24 frame signal example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 25 order of register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 26 8-bit p access interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 27 16-bit p access interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 28 initialization procedure after reset . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 29 h.100 master and slave configuration process . . . . . . . . . . . . . . . . 109 figure 30 example: input bit shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 31 example: output bit shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 32 example framing groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 33 example: 8-bit connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 34 subchannel address in time-slot . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 35 example: 4-bit connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 36 example: 2-bit connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 37 example: 1-bit connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 38 example: broadcast connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 39 example: subchannel broadcast connection . . . . . . . . . . . . . . . . . . 121 figure 40 example: multipoint connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 41 example: send message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 42 pcm timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 43 parallel mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 pef 20451 / 20471 / 24471 preliminary data sheet 2001-11-16 list of figures page figure 44 h-bus and pcm (local bus) clock alignment . . . . . . . . . . . . . . . . . . 132 figure 45 h-bus frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 46 h.1x0 detailed functional timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 47 h.1x0 functional timing for 8, 4 and 2 mbit/s data streams . . . . . . 133 figure 48 detailed data bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 49 clock skew timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 50 sclk-d timing for scbus operating at 8.192 mbit/s . . . . . . . . . . . . 137 figure 51 infineon/intel read cycle in de-multiplexed mode . . . . . . . . . . . . . . 139 figure 52 infineon/intel write cycle in de-multiplexed mode . . . . . . . . . . . . . . 139 figure 53 infineon/intel read cycle in multiplexed mode . . . . . . . . . . . . . . . . . 140 figure 54 infineon/intel write cycle in multiplexed mode . . . . . . . . . . . . . . . . . 141 figure 55 motorola read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 56 motorola write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 57 boundary scan timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 58 hardware reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 59 external crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 60 i/o wave form for ac-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 61 outlines of p-bga-217-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 pef 20451 / 20471 / 24471 preliminary data sheet 2001-11-16 preliminary table 1 who should read what? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 2 switi family tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 3 h.100/h.110 bus interface (h-mode only) . . . . . . . . . . . . . . . . . . . . . . 16 table 4 local bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5 gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6 clock pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10 stream-to-stream connection mapping . . . . . . . . . . . . . . . . . . . . . . . 28 table 11 data rates for local and h-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 12 maximum possible data rates for htsi in m-mode . . . . . . . . . . . . . . . 49 table 13 maximum possible data rates for htsi in h-mode . . . . . . . . . . . . . . . 49 table 14 tap controller instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 15 boundary scan idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 16 idcode via p read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 17 register overview for 8-bit interface . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 18 value range for spa/dpa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 19 value range for itsa/otsa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 20 value range for sca. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 21 register overview for 16-bit interface . . . . . . . . . . . . . . . . . . . . . . . . 90 table 22 affected registers for connection commands . . . . . . . . . . . . . . . . . . 99 table 23 affected registers for configuration commands. . . . . . . . . . . . . . . . 100 table 24 connection command and parameter codes . . . . . . . . . . . . . . . . . . 102 table 25 configuration command 1 and parameter codes . . . . . . . . . . . . . . . 103 table 26 configuration command 2 and parameter code. . . . . . . . . . . . . . . . 104 table 27 pcm timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 28 pcm parallel mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 29 component timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 30 clock skew timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 31 sclk-d timing at 8.192 mbit/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 32 infineon/intel timing in de-multiplexed mode . . . . . . . . . . . . . . . . . . 138 table 33 infineon/intel timing in multiplexed mode . . . . . . . . . . . . . . . . . . . . . 140 table 34 motorola timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 35 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 36 hardware reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 37 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 38 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 39 external capacitances for crystal (recommendation) . . . . . . . . . . . 149 table 40 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 41 input/output capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 pef 20451 / 20471 / 24471 preliminary data sheet 1 2001-11-16 preliminary preface the switching ic (switi) is a family of switching devices for a wide area of telecommunication and data communication applications. this document provides complete reference information according to chip interfaces, programming, internal architecture and applications. organization of this document this preliminary data sheet is divided into 9 chapters. it is organized as follows: chapter 1 , overview gives a general description of the product and of the switi family, lists the key features, and presents some typical applications. chapter 2 , pin description lists pin locations with associated signals, categorizes signals according to function, and describes signals. chapter 3 , architectural description rough overview of the internal architecture and clock fallback feature. chapter 4 , description of interfaces short introduction of used interfaces. chapter 5 , register description gives information about all registers accessible via the microprocessor interface according to address, short name, access, reset value and value range. chapter 6 , programming the device gives a variety of examples how to programm the device, lists all available command and parameter values. chapter 7 , timing diagrams contains timing diagrams. chapter 8 , electrical characteristics specification of the electrical parameters. chapter 9 , package outlines outlines of the available packages (p-bga-217-1). pef 20451 / 20471 / 24471 preliminary data sheet 2 2001-11-16 preliminary related documentation h.100 hardware compatibility specification: ct bus, revision 1.0 h.110 hardware compatibility specification: ct bus, revision 1.0 pci specification, revision 2.1, pci special interest group compact pci specification - picmg 2.0, revision 2.1 compact pci hot swap specification - picmg 2.1, revision 1.0 h-mvip standard, release 1.1a, go-mvip inc., january 1997 mvip-90 standard, release 1.1, go-mvip inc., october 1994 sc-bus specification, ansi/vita 6-1994 table 1 who should read what? addressed person relevant chapters programmer 3, 5, 6 board designer 2, 3, 4, 7, 8, 9 pef 20451 / 20471 / 24471 overview preliminary data sheet 3 2001-11-16 preliminary 1overview the new switching family, called switi, provides a complete and cost-effective solution for all switching systems. the family is divided in two sub-families, the mtsi family and the htsi family. the preliminary data sheet describes the functionality and characteristic of the htsi devices. the devices can be used in today ? s switching applications, e.g. conventional pbxs and central offices (co ? s), as well as in h.100/h.110 applications (only the htsi family), which are the key to high performing cti- and voice-over-ip-applications, one of the most important future technologies in telecommunications. the main requirements of today ? s switching applications are met by the following features: constant delay e.g. to support wide band data switching, or channel bundling bit switching/subchannel switching to support applications such as mobile base stations, dect, computer telephony in addition, the switi family provides new features to ensure a broad range of configurations to make it possible to adapt the device to all switching applications: a compliant h.100/h.110 interface (htsi) 8-channel stream-to-stream switching capability (htsi) message mode, which allows to assign a preset value to any output time-slot gpio (general purpose i/o) port, which is controlled from the external p switi family. the switi family consists of 6 ics with different switching capacities. the possible configurations are shown in table 2 . the htsi versions provide an additional h.100 / h.110 interface, while the mtsis are standard switching devices. all devices can be programmed easily, thus helping the designer/programmer to integrate the device into his application comfortably. table 2 switi family tree name package sales code connec- tions local bus in/out h-bus i/o htsi-xl (h-mode) p-bga-217-1 pef 24471 htsi-xl 2048 16/16 32 htsi-xl (m-mode) pef 24471 htsi-xl 32/32 - htsi-l (h-mode) p-bga-217-1 pef 20471 htsi-l 1024 16/16 32 htsi-l (m-mode) pef 20471 htsi-l 32/32 - pef 20451 / 20471 / 24471 overview preliminary data sheet 4 2001-11-16 preliminary htsi devices. the htsi devices can be operated in two different modes, h-mode and m-mode. in h-mode the device offers 16 local i/os and additionally a compliant h.100/h.110 interface (32 bidirectional i/os). the complete number of available connections can be assigned as h-bus to h-bus, local bus to local bus connection, or mixed. in m-mode all lines are configured as local i/os, so that in total 32 local i/os are provided. thus e.g. the htsi-xl device can be used as 2k non-blocking switch operating with all 32 i/os at 4.096 mbit/s. htsi (h-mode) p-bga-217-1 pef 20451 htsi 512 16/16 32 htsi (m-mode) pef 20451 htsi 32/32 - mtsi-xl p-mqfp-100-2 pef 24470 mtsi-xl 2048 16/16 - mtsi-l p-mqfp-100-2 pef 20470 mtsi-l 1024 16/16 - mtsi p-mqfp-100-2 pef 20450 mtsi 512 16/16 - table 2 switi family tree (cont ? d) name package sales code connec- tions local bus in/out h-bus i/o p-bga-217-1 preliminary data sheet 5 2001-11-16 switching ic switi pef 20451 / 20471 / 24471 version 1.3 cmos type package pef 20451 / 20471 / 24471 p-bga-217-1 preliminary 1.1 overview of features general switching capacity of 512, 1024, or up to 2048 connections of different types between different buses programmable data rates of 2.048 mbit/s, 4.096 mbit/s, 8.192 mbit/s, and 16.384 mbit/s on per stream basis constant delay or minimum delay programmable on per connection basis subchannel switching ability of 1-bit, 2-bit, 4-bit wide time-slots programmable clock shift for local bus 8-channel stream-to-stream switching for h.100/h.110 and interoperability bus automatic data rate adaption optional 8-bit parallel input and/or 8-bit parallel output for first 8 lines of local bus broadcast capabilities multipoint switching ability read and write access to all time-slots message mode (time-slot write access) programmable framing group gpio port 8-bit p-interface supports both intel and motorola mode optional 16-bit p interface mode (instead of gpio port) on chip pll for h.100/h.110, scbus, mvip, mvip-h clock operation (master/slave) and for local bus clock operation (master/slave) jtag interface ? boundary scan according to ieee 1149.1 3.3 v power supply 5 v tolerant inputs/outputs pef 20451 / 20471 / 24471 overview preliminary data sheet 6 2001-11-16 preliminary htsi in h-mode h.100/h.110 compliant interface with all mandatory signals local bus of up to 16 pcm ports (16 in/16 out) hot swapping htsi in m-mode local bus of up to 32 pcm ports (32 in/32 out). 1.2 features in detail flexible data rates each input and each output line of the local bus is programmable to operate at different data rates. the possible data rates are 2.048 mbit/s, 4.096 mbit/s, 8.192 mbit/s, and 16.384 mbit/s. even for the htsi in m-mode all of the 32 input lines and 32 output lines are configureable, except for the bit rate of 16.384 mbit/s. in case of 16.384 mbit/s only 24 lines can be used. the possible data rate for the data lines of the h-bus are 2.048 mbit/s, 4.096 mbit/s and 8.192 mbit/s. constant and minimum delay each connection independent of the addressed buses can be determined to be a constant delay or minimum delay connection. constant delay means that any input time- slot or subchannel is available on the programmed output after 2 frames. minimum delay means that the time-slot or subchannel appears at the output as soon as possible. the minimum delay depends on the chosen connections and the possible range is between 0 and 2 frames. subchannel switching each connection can be a 1-bit, 2-bit, 4-bit, or 8-bit connection. subchannel switching is applicable to both the local bus and the h-bus and has a constant delay of 2 frames. sub-channel switching is supported only for data rate of 2.048 mbit/s, 4.096 mbit/s and 8.192 mbit/s. programmable clock shift the position of time-slot 0 of each local bus input line can be programmed within the time-slot before and after the pfs rising edge in half clock steps. also the position of time-slot 0 of all local bus output lines can be programmed within the first time-slot after the pfs rising edge. pef 20451 / 20471 / 24471 overview preliminary data sheet 7 2001-11-16 preliminary 8-channel stream-to-stream switching this feature offers the possibility to efficiently switch one data stream to another at the same or different data rates without occupying switching memory capacity. it mainly supports interoperability between ct-bus (computer telephony) devices such as scbus and mvip-90 running at different data rates. it is possible to use up to 8 lines from the h.1x0 data lines to establish the connections. input and output frequency can be configured differently. automatic data rate adaption connections are also possible between lines operating at different data rates. the programmer just specifies input and output line, time-slot, and if necessary, the subchannel. parallel mode the first 8 local bus input and output lines can be configured to one parallel input or output port respectively. in serial mode a time-slot is determined by 8 consecutive data clock cycles according to each line. in parallel mode a time-slot is determined by 1 data clock cycle according to the first 8 lines. broadcast with this feature it is possible to distribute one incoming time-slot to different output time- slots. multipoint multipoint connections can be seen as the opposite of broadcast connections. here it is possible to generate one output time-slot consisting of several input time-slots. the specified input time-slots are logically and or or connected (selectable) and have a constant delay of 2 frames. read access the programmer has access to any input time-slot. after issuing an appropriate command the arrival of the time-slot will be reported by interrupt. the value can be read from a dedicated register. for every read request the command has to be issued again. message mode (write access) this feature allows a constant value to be sent to any given output time-slot. pef 20451 / 20471 / 24471 overview preliminary data sheet 8 2001-11-16 preliminary framing group it is possible to specify up to 8 different framing signals of 8 khz. the position of the rising edge and the pulse width can be programmed for each signal. the reference frame is determined by the pfs signal. the pulse parameters are programmed in half step resolution according to a 16.384 mhz clock. general purpose clocks all 8 gpclk lines can be configured as individual clock outputs with 8 khz, 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz and for test purposes with the internal frequency or the input frequency of the analog pll (apll). gpio port each line of the general purpose input/output port can be configured to be either input or output. according to an input an edge causes an interrupt. the outputs can be influenced by write access via the microprocessor interface. thus the user has the possibility to observe and influence additional signals for his application. microprocessor interface all devices provide a standard 8-bit microprocessor interface operating in either intel or motorola mode. optionally it is possible to configure the gpio port as additional data lines to provide a 16-bit microprocessor interface. the use of the 16-bit p interface reduces the number of write cycles required to configure a connection from 7 (in case of 8-bit p interface) to 3 write cycles. input/output tolerance the htsi can be used in a 5 v environment with two additional 5 v (vdd) power supply pins. local input and outputs are 3.3 v and 5 v tolerant. the outputs have ttl level driving capability. the h-bus lines of the htsi can be used in a 3.3 v signaling pci environment. pef 20451 / 20471 / 24471 overview preliminary data sheet 9 2001-11-16 preliminary 1.3 logic symbol the htsi is dedicated to perform time-slot switching between the local bus and the h- bus or to offer a solution for applications with a high number of local i/os. the htsi operates in two modes. in h-mode ( figure 1 ) it works with the h-bus and in m-mode ( figure 2 ) it operates without the h-bus. the htsi in h-mode provides 16 pcm input lines and 16 pcm output lines and the complete h-bus with 32 bidirectional h.100/h.110 data lines. figure 1 logic symbol: htsi in h-mode htsi pef 20451/20471/24471 v ss v dd d[7:0] a[4:0] ds rd wr r/w ct_d[31:0] /ct_frame_a ct_c8_a ct_c8_b /ct_frame_b ct_netref(_1) /fr_comp sclk c2 /c16+ /c4 tdi tdo tck tms cs ireq in[15:0] out[15:0] pfs pdc ale mode16 trst gpio general purpose clocks /c16- ct_netref_2 /ct_en /ct_reset sclkx2* / sclk-d ireq reset misc. switi_002.emf pef 20451 / 20471 / 24471 overview preliminary data sheet 10 2001-11-16 preliminary if no h-bus is needed it is possible to configure the htsi in m-mode. in this mode, the htsi provides 32 pcm input lines and 32 pcm output lines. figure 2 logic symbol: htsi in m-mode htsi pef 20451/20471/24471 v ss v dd in[31:0] out[31:0] pfs pdc gpio general purpose clocks ds rd wr r/w cs ireq ale mode16 tdi tdo tck tms trst d[7:0] a[4:0] reset ireq misc. switi_003.emf pef 20451 / 20471 / 24471 overview preliminary data sheet 11 2001-11-16 preliminary 1.4 typical applications typical applications of the switi family are: pcm switch, concentrator or multiplexer in pbxs, cos or mobile base stations h.100/h.110 interface in ? computer telephony systems ? internet telephony systems ? lan/wan access devices ? enhanced service platforms the following sections give a general overview of the system integration of the switi family. 1.4.1 standard pbx or co application the mtsi or the htsi in m-mode can be used, just as the mtsc or mtsl, in standard private branch exchange or central office applications ( figure 3 ), e.g. in the switching network. figure 3 standard pbx or co application line unit epic/ delic switching network coordination processor cp hdlc pcm mtsi/ htsi pbx or co mtsi/ htsi pcm pcm slmd subscriber line modul digital epic/ delic switi_014.emf pef 20451 / 20471 / 24471 overview preliminary data sheet 12 2001-11-16 preliminary 1.4.2 computer telephony application in computer telephony integration (cti) applications, resources such as the analog telephone line cards, isdn ports, switching controllers, fax firmware, or voice processing modules are in the form of plug-in cards that sit on the isa or pci slots of a pc. resource sharing is established by connecting the top of the plug-in cards with cables. this time division multiplex (tdm) bus has evolved from the original h-mvip, mvip-90, dialogic's sc-bus, into the latest h.100/h.110 bus or h-bus developed by the enterprise computer telephony forum (ectf). by connecting to the h.100/h.110 interface devices, system modules may send and receive data to and from any one of the 4096 tdm time-slots of the h-bus. the h-bus also offers the ideal solution for routers to provide a bridge between the data communication and telecommunication system modules. in computer telephony (ct) environment, resource sharing is accomplished by passing data back and forth through the h.100/h.110 bus. figure 4 shows the example. figure 4 ct application h.100/h.110 line cards htsi htsi htsi dsp voice recognition base transceiver station (bts) htsi switi_010.emf pef 20451 / 20471 / 24471 overview preliminary data sheet 13 2001-11-16 preliminary 1.4.3 router / remote access application the htsi (h-mode) or also the mtsi (if no h-bus interface is used in the system) is used in multivoice applications as the bridge connecting the data communication modules to the telecommunication modules in a router/remote access design. figure 5 shows the example. figure 5 router / remote access applications modem pool server htsi h.100/h.110 pcm/iom-2 htsi lan htsi htsi falc54 (framer) codec munich32 (hdlc) lan switi_009.emf pef 20451 / 20471 / 24471 overview preliminary data sheet 14 2001-11-16 preliminary 1.4.4 voice over ip application in a voice over ip application ( figure 6 ) the htsi (in h-mode) may be used to connect a conventional pbx to the h-bus. a vocoder card, also connected to the h-bus, performs speech compression and decompression whereas an ethernet card transmits and receives the compressed data over the network. figure 6 voice over ip application pbx h.100/ h.110 processor vocoder pcm pci/cpci ethernet lan/wan htsi htsi e1/t1 switi_004.emf pef 20451 / 20471 / 24471 pin description preliminary data sheet 15 2001-11-16 preliminary 2 pin description the pin description gives an overview of the pin numbers, names, direction, position and function ordered by the different interfaces. note: all unused input or i/o pins should be connected to v ss to avoid leakage current. 2.1 pin diagram figure 7 pin configuration nc nc ct_d_0 /in_16 in_3 in_5 vss in_9 in_11 vdd nc nc nc vss vdd in_1 vdd5 in_6 in_7 vdd5 in_12 in_14 nc vss nc gpclk_2 nc vss vss in_2 vss in_4 vdd in_8 vss vss vss vdd wr r/w vdd /ct_ frame_a gpclk_0 vss in_0 vdd vss vdd in_10 in_13 in_15 vss vss c2 a_1 p-bga- 217-1 gpclk_5 vss gpclk_3 gpclk_1 rd/ds a_0 a_2 vdd gpclk_7 gpclk_6 ct_c8_a gpclk_4 bottom view ale /c4 vss /c16+ vssa vdda /ct_ frame_b ct_c8_b a_4 a_3 d_0 d_2 eclko m-mode ct_ netref2 vdd vdd d_1 d_3 /c16- eclki reserv. reserv. vss vss d_4 vdd vss h110- mode /ct_ reset ntw k_2 vdd vdd d_6 /fr_ comp d_5 ntw k_1 vdd reset ireq gpio_1 sclk gpio_0 d_7 vss mode16 vdd ct_ netref1 gpio_5 gpio_3 vss vdd cs vss pfs tdo vdd gpio_6 sclkx2* sclk-d gpio_2 pdc trst tms vss vss vdd vss vdd out_10 out_13 vss vss gpio_7 gpio_4 tdi tck vss vdd out_1 vdd5 out_4 vdd vss vdd out_15 vss nc /ct_en nc vss nc out_3 out_5 vss out_9 out_11 vss ct_d_31 /out_31 vss nc nc nc out_0 out_2 vss out_6 out_7 out_8 vdd5 out_12 out_14 nc nc a b c d e f g h j k l m n p r t u vss vss vss vss vss vss vss vss vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ct_d_30/ out_30 ct_d_29/ out_29 ct_d_28/ out_28 ct_d_27/ out_27 ct_d_26 /out_26 ct_d_25/ out_25 ct_d_24 /out_24 ct_d_23 /out_23 ct_d22/ out22 ct_d_21 /out_21 ct_d20/ out20 ct_d_19/ out_19 ct_d_18/ out_18 ct_d_17/ out_17 ct_d_16/ out_16 ct_d_1/ in_17 ct_d_2/ in_18 ct_d_3/ in_19 ct_d_4/ in_20 ct_d_5/ in_21 ct_d_6/ in_22 ct_d_7/ in_23 ct_d_8/ in_24 ct_d_9 /in_25 ct_d_10 /in_26 ct_d_11 /in_27 ct_d_12 /in_28 ct_d_13 /in_29 ct_d_14/ in_30 ct_d_15/ in_31 switi_076.em f p-bga-217-1 pef 20451 / 20471 / 24471 pin description preliminary data sheet 16 2001-11-16 preliminary 2.2 pin definitions and functions 2.2.1 h-bus interface the following table ( table 3 ) is only applicable for the h-mode except the ct_d (in/ out) lines. table 3 h.100/h.110 bus interface (h-mode only) pin no. symbol in (i) out (o) function reset behavior d16 c t_frame_a i/o h.1x0 only frame sync - driven by the "a" clock master. this is a negative true pulse, nominally 122 ns wide that straddles the beginning of the first bit of the first time slot. it has a period of 125 s. high z f15 ct_c8_a i/o h.1x0 only bit clock - driven by "a" clock master. the clock frequency is 8.192 mhz. the duty cycle of this signal is nominally 50%. high z g15 c t_frame_b i/o h.1x0 only redundant frame sync - driven by the "b" clock master. this is a negative true pulse, nominally 122 ns wide that straddles the beginning of the first bit of the first time slot. it has a period of 125 s. high z g14 ct_c8_b i/o h.1x0 only redundant bit clock - driven by "b" clock master. the clock frequency is 8.192 mhz. the duty cycle of this signal is nominally 50%. high z t3, p5, t4, r5, u5, r7, u6, t8, t9, r9, u11, p11, u12, t13, p12, t14, c4, a3, c5, a4, b6, c7, b7, a8, a9, a10, b11, d11, b12, a14, d12, a15 ct_d[31:0] 1) ct_d[15:0] as in[31:16] ct_d[31:16] as out[31:16] i/o i o h-mode serial data lines that can be driven by any board in the system. however, only one board can drive the bus at any given time slot on each stream. each signal contains 128 time slots per frame at a clock frequency of 8.192 mhz. these 32 signals collectively are referred to as the ct_d bus. ct bus devices may connect to subsets of the ct_d bus. m-mode pcm receive data port 16 to 31 (pcm mode only) pcm transmit data port 16 to 31 (pcm mode only) high z high z pef 20451 / 20471 / 24471 pin description preliminary data sheet 17 2001-11-16 preliminary m14 ct_netref_1 i/o h.1x0 additional network timing reference - driven by any (single) ct bus digital trunk interface to provide network synchronization to the ct bus. this signal can have any duty cycle as long as the period is 125 s (8 khz), 647 ns (1.544 mhz), or 488 ns (2.048 mhz) and is network synchronized. there is no specified phase relation to ct_netref_2 and the other clocks. it has a minimum high of 90 ns and a minimum low time of 90 ns. high z h15 ct_netref_2 i/o h.1x0 additional network timing reference - driven by any (single) ct bus digital trunk interface to provide network synchronization to the ct bus. this signal can have any duty cycle as long as the period is 125 s (8 khz), 647 ns (1.544 mhz), or 488 ns (2.048 mhz) and is network synchronized. there is no specified phase relation to ct_netref_1 and the other clocks. it has a minimum high time of 90 ns and a minimum low time of 90 ns. high z r1 ct_en i h.110 only logic low signal to indicate that j4 of a ct bus card is fully seated. k16 ct_reset i h.110 only logic low signal used to reset all ct bus cards that do not have access to the pci rst# reset from j1/p1. k2 fr_comp i/o h.1x0 compatibility frame pulse - driven by current clock master. this is a negative true pulse, nominally 122 ns wide, that straddles the beginning of the first bit of the first time slot. it has a period of 125 s. this signal serves as the frame synchronization signal for scbus (fsync*) and mvip (/f0). high z l3 sclk i/o h.1x0 scbus system clock - driven by current clock master. the clock is selectable. it can be either 2.048 mhz, 4.096 mhz, or 8.192 mhz. it is used to identify the data bit positions on the scbus. the positive going edge indicates the beginning of the bit. high z n2 sclkx2* sclk-d i/o h.100 scbus system (sclk) clock times two - driven by current clock master. the clock frequency is exactly twice that of sclk. transitions of sclk occur on the falling edge of sclkx2* for scbus operating at 2.048 mhz, 4.096 mhz, or 8.192 mhz. h.110 inter-operability clock - driven by current clock master. the clock frequency is 8.192 mhz. it is used to identify the data bit positions on the ansi vita 6, scbus. the positive going edge indicates the sample point of the bit. high z table 3 h.100/h.110 bus interface (h-mode only) (cont ? d) pin no. symbol in (i) out (o) function reset behavior pef 20451 / 20471 / 24471 pin description preliminary data sheet 18 2001-11-16 preliminary d2 c2 i/o h.1x0 mvip-90 bit clock - driven by current clock master. the clock frequency is 2.048 mhz, nominally symmetrical. the positive going edge indicates the beginning of the bit. high z f3 c4 i/o h.1x0 mvip-90 bit clock times two - driven current by clock master. the clock frequency is exactly twice c2, and transitions of c2 are synchronous with the falling edge of c4 . high z f1 c16 +i/oh.1x0 h-mvip 16.384 mhz positive active low clock. high to low transition on frame boundary high z h1 c16 -i/oh.1x0 h-mvip 16.384 mhz negative active low clock. low to high transition on frame boundary high z h16 m-mode 2) i mode selection pin for h-mode or m-mode low=h-bus is in normal h.100/h.110 mode (h-mode) high=h-bus interface is additional pcm interface (port 16 to 31), (m-mode) k17 h110-mode 3) i mode selection pin for h.100/h.110 low = the h-bus operates in h.100 mode high = the h-bus operates in h.110 mode note: the pin must be connected to vss in m- mode 1) t3 is ct_d31, p5 is ct_d30, t4 is ct_d29.. 2) pin has to be connected to vdd or vss as required. the pin information is sampled during reset. 3) pin has to be connected to vdd or vss as required the pin information is sampled during reset. the pin must be connected to vss in m-mode. table 3 h.100/h.110 bus interface (h-mode only) (cont ? d) pin no. symbol in (i) out (o) function reset behavior pef 20451 / 20471 / 24471 pin description preliminary data sheet 19 2001-11-16 preliminary 2.2.2 local bus interface (pcm) 2.2.3 general purpose port table 4 local bus interface pin no. symbol in (i) out (o) function reset behavior n15 pfs i/o pcm frame synchronization clock of 8 khz high z p17 pdc i/o pcm data clock of 2.048 mbit/s, 4.096 mbit/s, 8.192 mbit/s, 16.384 mbit/s high z d5, b4, d6, b5, a6, d7, a7, c9, b9, b10, a12, c11, a13, c13, b14, d13 in[15:0] 1) 1) d5 is in15, b4 is in14, d6 is in13.. i pcm receive data port 15 to 0 r4, u3, p6, u4, t6, p7, t7, u8, u9, u10, t11, r11, t12, u14, r13, u15 out[15:0] 2) 2) r4 is out15, u3 is out14, p6 is out13.. o pcm transmit data port 15 to 0 high z table 5 gpio pin no. symbol in (i) out (o) function reset behavior p2, n3, m4, p1, m3, n1, l4, l2 gpio[7:0] 1) d[15:8] 1) p2 is gpio7, n3 is gpio6, m4 is gpio5.. i/o general purpose i/o port (only if 8-bit p interface used) upper 8 bit of 16-bit p interface input pef 20451 / 20471 / 24471 pin description preliminary data sheet 20 2001-11-16 preliminary 2.2.4 clock signals 2.2.5 jtag interface table 6 clock pins pin no. symbol in (i) out (o) function reset behavior j17 eclki i external crystal input of 16.384 mhz, or 32.768 mhz external oscillator input of 16.384 mhz, or 32.768 mhz h17 eclko o external crystal output of 16.384 mhz, or 32.768 mhz f17, f16, e17, f14, e15, c17, e14, d15 gpclk[7:0] 1) 1) f17 is gpclk7, f16 is gpclk6, e17 is gpclk5.. o general purpose clock output (framing signals) high z l17 ntwk_1 i primary network timing reference input optionally the pll can be synchronized to this input which can be 8 khz, 512 khz, 1.536 mhz, 1.544 mhz, 2.048 mhz k15 ntwk_2 i secondary network timing reference input optionally the pll can be synchronized to this input which can be 8 khz, 512 khz, 1.536 mhz, 1.544 mhz, 2.048 mhz table 7 jtag interface pin no. symbol in (i) out (o) function reset behavior r16 tck i test clock single rate test data clock. p15 tms i test mode select a ? 0 ? to ? 1 ? transition on this pin is required to step through the tap controller state machine. p16 trst itest reset resets the tap controller state machine (asynchronous reset). n14 tdo o test data out in the appropriate tap controller state test data or a instruction is shifted out via this line. high z r17 tdi i test data input in the appropriate tap controller state test data or a instruction is shifted in via this line. pef 20451 / 20471 / 24471 pin description preliminary data sheet 21 2001-11-16 preliminary 2.2.6 microprocessor interface table 8 microprocessor interface pin no. symbol in (i) out (o) function reset behavior n17 cs i chip select active low. a "low" on this line selects all registers for read/ write operations. e4 rd ds i read (intel/infineon mode) indicates a read access. data strobe (motorola mode) during a read cycle, ds indicates that the device should place valid data on the bus. during a write access, ds indicates that valid data is on the bus. c1 wr r/w i write (intel/infineon mode) indicates a write access. read/write (motorola mode) indicates the direction of the data transfer on the bus. f4 ale i address latch enable controls the on-chip address latch in multiplexed bus mode. while ale is ? high ? , the latch is transparent. the falling edge latches the current address. ale is also evaluated to determine the bus mode (ale fix ? low ? = motorola, fix ? high ? = intel/infineon) m16 mode16 i microprocessor bus 8/16-bit interface selection ( ? low ? = 8 bit, ? high ? = 16 bit) l14 ireq/ ireq o od interrupt request this pin is programmable to push/pull (active high or low) or open-drain. this signal is activated when switi requests an p interrupt. when operated in open drain mode, multiple interrupt sources may be connected. high z g4, g3, e2, d1, e3 a[4:0] 1) 1) g4 is a4, g3 is a3, e2 is a2.. i address bus when operated in address/data multiplex mode, the address pins are externally connected to the d bus. l1, k3, k1, j3, h2, g1, h3, g2 d[7:0] 2) 2) l1 is d7, k3 is d6, k1 is d5.. i/o data bus input l15 reset i system reset switi is forced to go into reset state. pef 20451 / 20471 / 24471 pin description preliminary data sheet 22 2001-11-16 preliminary 2.2.7 power supply table 9 power supply pins pin no. symbol in (i) out (o) function c2, e1, j2, m1, n4, r6, r10, r14, m15, d17, b15, c10, a5, d8, d10, h4, h14, k4, p8, p10, k14, l16 v dd i power supply 3.3 v b8, b13, r12, u7 v dd5 i i/o reference voltage 5,0 v for 5 v tolerant i/os. pins must be connected at 3,3 v in a 3,3 v signal environment d3, f2, j1, m2, p3, t5, r8,t10, u13, p13, n16, m17, e16, c14, c12, a11, c8, c6, b2, b16, c3, c15, d4, d9, d14, h8, h9, h10, j4, j8, j9, j10, j14, k8, k9, k10, p4, p9, p14, r3, r15, t2, t16 v ss i digital ground (0 v) g16 v dda i power supply analog logic 3.3 v used for pll g17 v ssa i analog ground (0 v) j16 r reserved. must be connected to vss j15 r reserved. must be connected to vss b1, r2, u2,t15, t17, c16, a16, b3, a1, t1, u1, u16, u17, b17, a17, a2 nc not connected pef 20451 / 20471 / 24471 architectural description preliminary data sheet 23 2001-11-16 preliminary 3 architectural description the following sections give a short overview of the functionality of the switi. 3.1 functional block diagram figure 8 block diagram output data memory input data memory minimum delay constant delay / subchannel control control control local i/os p-interface pll clocks jtag gpios switching factory switi_078.emf i/o block w. autom atic data rate adaption input handler programming line, ts h.1x0 bus h.1x0 i/os local bus output handler line, ts pef 20451 / 20471 / 24471 architectural description preliminary data sheet 24 2001-11-16 preliminary 3.2 overview of functional blocks switching factory the switching factory is responsible for transferring and handling the incoming data streams to the assigned output channels and time-slots. the block includes a 512, 1024, or 2048 byte input and output data memory as far as an input and output connection memory. local bus and h-bus i/o block the block is designed to handle the conversion of the data provided via the switching block and the external pcm and h.1x0 interface. it performs the pcm and h.1x0 timing, the data rate selection and the tristate control. microprocessor interface block a standard 8-bit multiplexed or de-multiplexed p interface is provided, compatible to intel/infineon tech. (e.g. 80386ex, c166) and motorola (e.g. 68040, 68340, 68360, 801) bus systems. if the gpio port is not needed it can be used to provide a 16-bit p interface. gpio block this block supports up to 8 external port lines each one configurable as input or output. a change on an input line may cause an interrupt (if not masked). the user has access to the port configuration and information via the appropriate registers of the p interface. pll and clock block the pll generates all frequencies supporting the h.1x0, scbus, mvip, h-mvip busses. the internal phase-locked loop (pll) generates all bus frequencies synchronized to a selected reference signal. the output frequency tolerance is equal to the input frequency tolerance. the pll operates from a 16.384 mhz, or 32.768 mhz external crystal, oscillator. according to the h.1x0 specification the input frequency tolerance must be 32 ppm or less. pef 20451 / 20471 / 24471 architectural description preliminary data sheet 25 2001-11-16 preliminary 3.3 switching factory as shown in figure 8 the switching factory comprises the input/output data memory and the input/output data handler with the programmed connections. the i/o controller handles all lines operating at the same or different data rate. to establish a connection the user must only program the source line with time-slot and the destination line with the time-slot. the internal controller (data handler) writes the connection in a connection descriptor list and stores this list in the connection data handler. the programming procedure is described in chapter 6 . the incoming time-slot will be stored in the input data memory controlled by the input handler. the output handler controls the constant, minimum delay and subchannel switching. 3.3.1 switching modes the switi family supports a various number of switching modes. all modes are described in the following chapters. 3.3.1.1 minimum and constant delay each connection independent of the addressed buses can be determined to be a constant delay or minimum delay connection. constant delay means that any input time- slot or subchannel is available on the programmed output after 2 frames. minimum delay means that the time-slot or subchannel appears at the output as soon as possible. the minimum delay depends on the chosen connections and the possible range is between 0 and 2 frames, up to 3 frames in rare cases. an application note which describes the possible connection and minimum delays is available. 3.3.1.2 subchannel switching subchannel switching is applicable to both the local bus and the h-bus and has a constant delay of 2 frames. every connection can be 1-bit, 2-bit, 4-bit, or normal 8-bit connection. it is possible to combine every kind of subchannel connection, e.g. two 1-bit time-slots with one 4-bit time-slot to one output time-slot. please refer to chapter 6.11.2 for a detailed description about the programming. 3.3.1.3 multipoint switching as described in the overview the multipoint-switching allows to switch several input time- slots to one output time-slot. all input data are logical and or or connected. this mode is selectable with the multipoint connection command. the setup (logical and or or) for the last connection determines all other previous programmed multipoint connections. multipoint switching has always a constant delay. subchannel switching is not supported. pef 20451 / 20471 / 24471 architectural description preliminary data sheet 26 2001-11-16 preliminary 3.3.1.4 broadcast switching broadcast switching allows to distribute one incoming time-slot to different output time- slots. the input and output mechanism is the same as the normal constant delay connection mode with subchannel switching. minimum delay is also supported without subchannel switching. a table with the possible connections and minimum delays will be provided. the broadcast connection is programmed in the same way as a normal connection. the output time-slots can be released with the disconnect part of broadcast command. the last connection must be released with the normal disconnect command. subchannel broadcast it is possible to program one input time-slot as broadcast subchannel connections. that means the bits from the input time-slot are used in several broadcast connections related to one ore more output time-slots. the output time-slots must be released with the disconnect part of broadcast command. the last subchannel connection must be released with the normal disconnect command. (please refer to chapter 6.11.4 for an example) 3.3.1.5 bidirectional switching the input and output mechanism is the same as the normal constant delay or minimum delay connection. the exception for the internal data handling is explained in the following figure. since the internal state machine has to calculate the belonging connection the time to program a bidirectional connection is twice as the time to program a normal connection. there is a special command to program a bidirectional connection. a bidirectional connection can only be programmed on a available time-slot and input/ output line. pef 20451 / 20471 / 24471 architectural description preliminary data sheet 27 2001-11-16 preliminary figure 9 bidirectional mode 3.3.1.6 stream-to-stream switching the stream-to-stream switching connection supports the interoperability for the h.1x0 bus with the mvip and scbus, it doesn ? t support the local bus lines. every dataline can be selected for the operation. the maximum number of switching channels is eight. the following example on page 29 is using two switching channels. the stream-to-stream connection can not be established parallel to the normal connections. the output of the stream-to-stream switch is multiplexed with the output of the switching factory, with the stream-to-stream having priority. every stream-to-stream connection must be programmed with the special command in the cmd1 register. to establish the connection the bit i2 must be set to 1 and to release the connection the bit i2 must be set to 0. if the bit i3 is set to 1 all stream-to-stream connections will be released. the str bit in the ista1 register indicates that one or more stream-to-stream connections are set (see also chapter 6.2 ). a internal control port 0 local bus port 1 local bus port 0 port 1 ts 10 ts 20 swap spa and dpa swap itsa and otsa ts 20 ts 10 port 0 port 1 ts 10 ts 20 spa = 1 itsa = 14 dpa = 0 otsa = a spa = 0 itsa = a dpa = 1 otsa = 14 issued command internal ccmd = 09 switi_067.emf minimum delay pef 20451 / 20471 / 24471 architectural description preliminary data sheet 28 2001-11-16 preliminary logic avoids a wrong selection of the possible stream-to-stream connections and thus prevents bus collisions. the main application of the stream switch is to provide an inter-rate exchange highway allowing legacy bus devices to exchange data even though they operate at different rates with a minimum delay of zero frames. the stream-to-stream connections starts with the first frame and the switching possibilities are determined by the highest bit rate and can be seen as a repetition of same time-slot (ts) connections from one data line to another data line. if the first ts switching sequence is finished it starts with the same sequence from the next available time-slots. table 10 shows the possible time-slot connections. table 10 stream-to-stream connection mapping input data stream rate output data steam rate mode partition time-slot connection 2.048 mbit/s 2.048 mbit/s 0 0 to 1, 1 to 2, 2 to 3, 3 to 4,....., 31 to 0 4.096 mbit/s 0 0 to 2, 1 to 4, 2 to 6, 3 to 8,....., 31 to 0 1 0 to 3, 1 to 5, 2 to 7, 3 to 9,....., 31 to 1 8.192 mbit/s 0 0 to 4, 1 to 8, 2 to 12, 3 to 16,...., 31 to 0 1 0 to 5, 1 to 9, 2 to 13, 3 to 17,...., 31 to 1 2 0 to 6, 1 to 10, 2 to 14, 3 to 18,...., 31 to 2 3 0 to 7, 1 to 11, 2 to 15, 3 to 19,...., 31 to 3 4.096 mbit/s 2.048 mbit/s 0 0 to 1, 2 to 2, 4 to 3, 6 to 4,....., 62 to 0 1 1 to 1, 3 to 2, 5 to 3, 7 to 4,....., 63 to 0 4.096 mbit/s 0 0 to 1, 1 to 2, 2 to 3, 3 to 4,....., 63 to 0 8.192 mbit/s 0 0 to 2, 1 to 4, 2 to 6, 3 to 8,....., 63 to 0 1 0 to 3, 1 to 5, 2 to 7, 3 to 9,....., 63 to 1 8.192 mbit/s 2.048 mbit/s 0 0 to 1, 4 to 2, 8 to 3, 12 to 4,....., 124 to 0 1 1 to 1, 5 to 2, 9 to 3, 13 to 4,....., 125 to 0 2 2 to 1, 6 to 2, 10 to 3, 14 to 4,....., 126 to 0 3 3 to 1, 7 to 2, 11 to 3, 15 to 4,....., 127 to 0 4.096 mbit/s 0 0 to 1, 2 to 2, 4 to 3, 6 to 4,....., 126 to 0 1 1 to 1, 3 to 2, 5 to 3, 7 to 4,....., 127 to 0 8.192 mbit/s 0 0 to 1, 1 to 2, 2 to 3, 3 to 4,....., 127 to 0 pef 20451 / 20471 / 24471 architectural description preliminary data sheet 29 2001-11-16 preliminary example: d0 = input stream with 2.048 mbit/s, d3 = output stream with 8.192 mbit/s, mode 2 d3 = input stream with 8.192 mbit/s, d1 = output stream with 4.092 mbit/s, mode 1 figure 10 example for stream-to-stream switching 3.3.1.7 message mode the message mode allows to send a predefined 8-bit data value in a defined time-slot on a dedicated destination port. message mode is started or stopped via register ccmd . the data value to be send is predefined in register mv . the time-slot and the destination port is is defined in register otsa and register dpa . 3.3.2 parallel mode for local bus the parallel mode can be set with the ? set parallel mode ? command in the configuration command register. this command set the first 8 input lines and the first 8 output lines of the local bus as parallel bus. the data rate for all lines must be 2.048 mbit/s. if the parallel mode is enabled all included lines will be set to 2.048 mbit/s automatically. if the parallel mode is disabled all lines will keep the data rate of 2.048 mbit/s until a new data rate will be programmed for the selected line. the internal s/p-converter is bypassed. the 8 bit data stream per time-slot is distributed on 8 data lines, one bit for every line. the least significant bit is assigned to line 0 and the most significant bit is assigned to line 7. to program a connection line 0 must be used for this special parallel data port. the bit shift value must only be programmed for port 0 and this value will be assigned to the other 7 ports automatically. the initialize sequence is described in chapter 6 . the switching data handling is the same as the data handling for constant delay or minimum delay mode. a timing diagram is provided in the timing diagram chapter (see ? pcm parallel mode timing ? on page 131 ). frame boundary 01 3 245 7 6 01 23 1 0 31 63 62 127 126 125 124 d0@2.048 mbit/s d1@4.096 mbit/s d3@8.192 mbit/s switi_059.emf pef 20451 / 20471 / 24471 architectural description preliminary data sheet 30 2001-11-16 preliminary 3.3.3 switching block error handling the normal procedure to establish a connection is explained in chapter 6 . the way to program a new connection for a specific time-slot and data line is to release the connection and to program the new connection. the switi switching concept provides an internal error handling to detect errors in the switching chain caused by a programming error. a programming error can occur because of noises on the data lines, software errors, etc. a programming error is defined as follows: ? if a non existing connection (minimum, constant delay, or message) will be released. ? or if a existing minimum delay connection will be established. if a programming error or a connection memory overflow is detected the interrupt bit con in the iesta2 register will be set. in this case the last connection which was tried to establish or to release is not valid. the switching mechanism is not affected and will continue with the switching process. for debug purposes the switi has the capability to write out the content of the complete connection memory and data memory via the microprocessor interface. this procedure is described in chapter 3.3.4 . it is recommended to track all established and connections with the specific customer application software. for debug purpose it is useful to compare the contents of the switching memory with the virtual connections in the application software. 3.3.4 analyze connection and data memory with the special command "memory dump enable" in the connection command register ( ccmd ) it is possible to read the complete memory in a defined sequence from the con register with a 8-bit p access. this feature can be used only for analyze purposes. the command disables the complete switching function as far as all data lines (pcm/ h.1x0) are set to high impedance. if the command is set and after the specific recovery time (200 ns) the connection chain and data memory can be read sequentially by a p access to the con register. the internal controller writes the next 8-bit memory data in the con register if the p read access is finished. that means there is a specific recovery time for the p to the next con read access. the internal memory dump controller reads the present memory contents of the input chain memory, data memory and output chain memory. during the memory dump the internal state machine will loose the synchronization with the external frame structure. therefore a software reset must be issued and the device must be programmed again, except the clock configuration. pef 20451 / 20471 / 24471 architectural description preliminary data sheet 31 2001-11-16 preliminary infineon technologies provides a software driver to recalculate the chain and to recover the current connections. for a detailed explanation of the internal structure and the software driver please refer to the application note ? connection memory dump ? . 3.4 clock generator and pll 3.4.1 general overview the following figure gives an overview about the clock generator with the integrated pll. figure 11 switi clock generator switi_058.emf h-mode pfs ct_netref_1 ct_netref_2 ntwk_1 ntwk_2 /fr_comp /ct_frame_a /ct_frame_b eclki eclko ct_c8_a ct_c8_b c2 /c16 apll cntr. logic 2.048mhz div : 1 : 2 : 4 : 8 frame sm ct_c8_a /ct_frame_a ct_c8_b /ct_frame_b main div norm. operation = 49.152 mhz apll bypass = 16.384/32.768 mhz 8.192m hz 8 khz h-mvip c2,/c4,/c16 /fr_comp mvip-90 c2,/c4 /fr_comp 4.096m hz 2.048m hz 16.384mhz scbus sclk, sclkx2 fsync pdc 2,4,8,16 mhz pfs 8 khz gpclk[7:0] ct_netref_1 ct_netref_2 ntwk_1 ntwk_2 ct_netref_2 ntwk_1 ntwk_2 ct_netref_1 div : 8 : 32 : 2048 osc htsi sclk c2,/c4,c16 sclk c2,/c4,c16 dpll #2 div : 4 div : 4 /c4 ct_c8_a/b slave path ref. clock mux pdc ct_c8_a/b 3 2 3 2 div : 1 : 2 : 4 : 8 : 64 : 192 : 193 div : 1 : 2 : 4 : 8 : 64 : 192 : 193 bypass gpclk[7:0] int. frequency input apll sclk sclkx2 div : 1 : 2 r eset = : 1 mux master/slave pcm div 16.384mhz 4.096mhz 2.048mhz 8 khz 8.192mhz 16.384mhz from main div div : 8 dpll #1 reset pdc pfs phase alignm ent frame alignm ent programmable h.1x0 automatic ct_frame_a ct_frame_b /fr_comp not used in m-mode pef 20451 / 20471 / 24471 architectural description preliminary data sheet 32 2001-11-16 preliminary the switi clock generator provides all necessary clock signals for the switi pcm (local bus) and h.1x0 interfaces. since the device is a h.1x0 master capable device there are two digital plls which can be locked to different network reference signals. the digital pll synchronizes the external crystal or oscillator to the selected reference clock. the digital pll (dpll) will be bypassed if the selected reference signal is >= 2.048 mhz. the input signal for the analog pll (apll) is 2.048 mhz in normal operation mode. the apll is used for multiplying the 2.048 mhz clock into a 49.152 mhz clock and to generate all clock signals for the pcm and h.1x0, and general purpose clock signals. the switi has an on-chip oscillator which allows the user to connect an external 16.384 mhz or 32.768 mhz crystal. instead of using the crystal it is possible to assign a 16.384 mhz, or 32.768 mhz oscillator to the eclki pin. after the power-on or hardware reset the apll is bypassed. the apll will be synchronized (after approximately 750 s) to the external crystal or external oscillator if the command ? set external frequency ? is set. this command must be used otherwise the internal working frequency is equal to the external input frequency and the switi will not work properly. if the apll is locked the status bit ? apll ? in the ista1 register will be set. note: after the reset it is necessary to program the correct crystal or oscillator value as first programming step. otherwise the operation frequency for the switi is not correct. 3.4.2 analog pll (apll) features low cycle-to-cycle jitter < 1 ns natural frequency f g = 15 khz damping factor = 0.7 input frequency = 2.048 mhz in any case output frequency = 49.152 mhz, duty-cycle = 50 % rule behavior = change of output frequency in range of 0 - 10% in response to changes of input frequency phase slope of output frequency equal to phase slope of input frequency note: it is necessary to provide a ?noise free? analog power (v dda /v ssa ) to reduce the internal jitter of the apll. these pins must be decoupled from the digital power (vdd/vss), see also the available application note ?layout notes?. pef 20451 / 20471 / 24471 architectural description preliminary data sheet 33 2001-11-16 preliminary 3.4.2.1 functional description figure 12 block diagram of apll the value of the output frequency depends of the programming of the n-divider. the chosen output frequency for the switi is 49.152 mhz and the input frequency is 2.048 mhz. the macro consists of a digital and an analog pll which are working together. during start-up only the digital one is enabled and makes a coarse adjustment, so that the technology dependency of the circuit is compensated. afterwards the digital pll is disabled again and the analog one is switched on for normal operation. the digital pll is of first order and consists of a frequency detector (fd), an up/down counter, a digital-to-analog converter (dac) and a current controlled oscillator (cco). the fd detects any frequency difference between the reference clock (fref: input clock fin = 2.048 mhz) and the divided oscillator clock. the output signal controls the counter. if the reference frequency is higher than the divided oscillator frequency the counter is increased. the counter output drives a current steering dac which controls the input current of the internal oscillator. its current rises and the output frequency increases until both frequencies are equal. the digital pll is enabled after reset or power up and is disabled after 750 s (lock time of pll). the counter keeps its value and the dac output current irough is constant until the digital pll is reseted. iref up/down counter dac charge pump cco n-divider vtoi frequency detector fin fref fref up/down cw incr decr iprop iint igrob fosc timer locked pu ibias ibias current reference phase/ frequency detector pef 20451 / 20471 / 24471 architectural description preliminary data sheet 34 2001-11-16 preliminary the second order analog pll consists of a phase/frequency detector (pfd), a charge pump (cp), a loop filter and the cco. the pfd which is sensitive to the rising edge detects any phase or frequency difference between the input clock (fref ) and the divided output clock (feedback ) and generates a control signal proportional to the phase difference. the output signals up and down cause the charge pump to modulate the amount of charge in the low pass filter (vtoi) for the integral part (iint ) and to feed current into the cco for the proportional part (iprop ). with these two currents and the dac output irough the cco is controlled. if feedback is leading fre f, the oscillator is too fast. the down signal is activated and the cp subtracts some current ipro p. when fref is in phase with the feedback the pll will hold the control current at that level and phase lock will be achieved. thus through this negative feedback arrangement, the pll causes the feedback and fref signals to be equal with minimum phase offset. if the analog pll becomes unstable, a signal pllko is generated which resets the digital pll. figure 13 apll - jitter transfer function 3.4.2.2 jitter-transfer-function jitter transfers or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. 0,1 0,2 0,3 0,4 1 234 10 0 +2 +4 +6 +8 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 f/f g 20lg |h(f)| pef 20451 / 20471 / 24471 architectural description preliminary data sheet 35 2001-11-16 preliminary figure 13 shows the jitter transfer function of the switi device. the cutoff frequency of the integrated low pass filter is f g =15khz. 3.4.3 master-slave selection for a proper working pll and clock fallback mechanism it is necessary to select the part as master or slave with the "select master/slave" command in the cmd1 register. if the m-mode is used it is not allowed ot use the special master command. as described in chapter 3.4.6 this command must be used to finish the clock generator configuration and/or to finish the h.1x0 fallback configuration. the pll reference source can be selected with the "pll primary reference for master selection" command, or with the "pll source selection" command. 3.4.4 phase alignment if the phase alignment function is enabled all pll output signals and the main divider are edge synchronized with the pll clock input. if the selected reference signal is less than 2.048 mhz the edge synchronization resolution depends on the selected external crystal/oscillator frequency. if the phase alignment function is disabled the pll output frequency (49.152 mhz) is edge synchronized with the pll input frequency and the main divider output frequencies are edge synchronized with pll output frequency. an example of phase alignment functionality is shown in figure 14 . phase alignment is required to keep the output signals in phase relative to the input signals (e.g. c8a relative to c8b). after reset phase alignment is automatically activated in secondary master and slave mode and turned off in master mode. note: the phase alignment should be disabled for all reference frequencies <2.048mhz. figure 14 example of phase alignment apll output (49.152 mhz) main divider output apll input (2.048 m hz) phase difference phase alignment enabled phase alignment disabled apll output (49.152 mhz) main divider output apll input (2.048 m hz) switi_091.emf pef 20451 / 20471 / 24471 architectural description preliminary data sheet 36 2001-11-16 preliminary 3.4.5 pll synchronization as shown in figure 11 there are several possibilities to synchronize the plls. for the synchronization it is necessary to distinguish between the different operational modes (h.1x0 with pcm, only pcm). the pll needs approximately 750 s to lock to the selected reference frequency. for the frame synchronization the clocking unit needs additionally two frames to synchronize the incoming frame with the generated frame. this frame synchronization will be enabled if the device is configured as h.1x0 slave, h.1x0 secondary master, and compatibility bus slave. 3.4.5.1 pll synchronization h-mode the following operational modes apply to the htsi h-mode. ? h.1x0 master and pcm master in this mode the reference frequency must be selected by software according the h.1x0 specification. the h.1x0 and pcm clock synchronization is guaranteed by the fact, that the synchronized 2.048 mhz clock, generated from one of the digital plls, is used as input clock for the analog pll, used for the generation of all necessary clocks. if the reference frequency is equal or higher than 2.048 mhz the digital pll is bypassed and the reference signal is connected with analog pll. the beginning of the pcm frame is equal with the beginning of the h.1x0 frame. ? h.1x0 slave and pcm master for the h.1x0 slave mode both digital plls are bypassed and the input signal for the analog pll comes from one of the selected slave path clock sources. the pcm clock signals are synchronized to the h.1x0 selected input reference clock signal and there isn ? t a phase difference between the signals. the beginning of the pcm frame is equal with the beginning of the h.1x0 frame. this is guaranteed by the fact, that the related frame signal to the selected clock signal is used for the frame synchronization. ? h.1x0 master and pcm slave this mode is not allowed, since the pcm frame start is not synchronized with the h.1x0 frame start. ? h.1x0 slave and pcm slave the pdc and pfs signals must be equal to the highest selected pcm datarate and must be sourced. the incoming pcm clock/frame signals must be derived from the same clocking source as the h.1x0 clocks or from a master with the same reference clock as the h.1x0 master. since there isn ? t a elasticity switching buffer in the switi the incoming clock must be synchronized, must have the same phase and the h.1x0 frame start must be equal to the pcm frame start. pef 20451 / 20471 / 24471 architectural description preliminary data sheet 37 2001-11-16 preliminary 3.4.5.2 pll synchronization m-mode the pll reference source can be selected from the primary reference master source (pfs, pdc, ntwk_1/_2). if the selected reference signal is less than 2.048 mhz the main digital pll is used to synchronize the analog pll. the digital pll is sourced from the external oscillator, or crystal. in this case the analog pll output frequency tolerance is equal to the external oscillator/crystal frequency tolerance. furthermore the analog pll can be sourced directly from the external oscillator, or crystal, or from the pdc input. all generated output frequencies will have the same tolerance as the selected input frequency. 3.4.6 pll error handling the switi in h-mode has an integrated control logic to detect possible pll configuration errors. if one of the errors (see below) occurred the clock fallback mechanism and the pll functionality is not guaranteed. the control mechanism starts with the command ? set as h.1x0 master/slave (htsi h-mode) ? in the cmd1 register. that means that the mentioned command finished the clock generator configuration. as shown in figure 11 there is a cntr. logic for the two apll multiplexer implemented. the first multiplexer is used to select one reference source for the master mode and the second multiplexer is used to decide between the slave or master path. the main task for this control logic is to make sure that the input signal for the apll derives from the internal oscillator (external oscillator) after the reset. the second task is to control the input signal for the apll during the normal operation and to decide whether the programmed combination is correct. if one of the following combinations occur, the control logic selects the internal oscillator, resets the complete clock generator configuration and an interrupt will be generated (-> wrong pll source programming). configuration errors which will be detected: htsi h-mode master configuration ? pll2 source was selected (slave path) htsi h-mode slave configuration ? pll main or secondary master reference was selected furthermore the fallback state machine controls the logic to multiplex the necessary signal for the fallback mechanism. since there are redundant paths for the reference clock and also for the slave clocks the clock fallback time depends only on the multiplexer delay time. 3.4.7 clock fallback this chapter must be read if the switi is used as h.1x0 device (h-mode). pef 20451 / 20471 / 24471 architectural description preliminary data sheet 38 2001-11-16 preliminary 3.4.7.1 clock signal monitoring to support the clock fallback mechanism the switi has the capability to monitor the ct_ca (ct_c8_a, ct_frame_a ), ct_cb (ct_c8_b, ct_frame_b ) clocks additional with the selected primary pll reference, and to monitor the interoperability clock signals. the switi reports every clock failure to the host with a interrupt if it is not masked. if the interrupt is masked the status of the clock errors can be read from the iesta1 and iesta2 registers (polling). the h.1x0 clock signal monitoring will start immediately after programming a new reference clock. the process is finished with the command ? master slave ? from the cmd1 register. the following monitoring requirements for h.1x0 must be meet: ? a received rising edge of ct_c8_a/b (both signals must controlled independently) doesn ? t arrive within 35ns of the expected edge. or ? there are not exactly 1024 clock periods per frame. if one of these requirements are not meet an interrupt will be generated (if not masked) to inform the system software that one of the clock circuits (a or b) is failed. the following monitoring requirements for the interoperability clock signals must be meet. the fr_comp is monitored in conjunction with the selected primary pll reference (master) signal or with the selected pll source (slave). mvip ? a received rising edge of c2, c4 , or c8, or c16 doesn ? t arrive within 40 ns of the expected edge. or ? there are not exactly 256, or 512, or 1024, or 2048 clock periods per frame scbus ? a received rising edge of sclk doesn ? t arrive within 40 ns of the expected edge. or ? there are not exactly 256 (sclk=2.048 mhz), 512, or 1024 clock periods per frame. ntwk signals a received rising edge of the ntwk signal doesn ? t arrive within 80 ns of the expected edge. pef 20451 / 20471 / 24471 architectural description preliminary data sheet 39 2001-11-16 preliminary 3.4.7.2 clock fallback mechanism the clock fallback mechanism can be switched on with the special command "h.1x0 fallback mechanism and clock monitoring" and the related instruction bits. as described in the h.1x0 specification there are two different fallback path ? s in the fallback state machine. the instruction "fallback from main to secondary reference (primary master)" in conjunction with the command "automatic switch back to main ref." covers the "primary ntwk link fails" path. the correct reference (main and secondary) as described in the h.1x0 specification must be programmed, e.g. ntwk or ct_netref. the instruction "fallback from main to secondary reference (secondary master)" and "from a clock to b clock (slave)" covers the "primary master clock circuit fails" path in the fallback state machine. figure 15 clock fallback of primary master the primary master is synchronized to a reference clock (ntwk or ct_netref) and drives the ct_c8_a and ct_frame_a clocks. figure 15 shows a configuration example. if the primary network reference clock (ntwk_1) fails the device automatically synchronizes to the secondary network reference clock (ntwk_2). if the primary reference clock returns the device may synchronize to it again automatically or by software command (depends on configuration). if not masked the failure is reported by an interrupt. ct_netref_1 ct_c8_a; ct_frame_a primary master ntwk_1 ct_netref_2 ntwk_2 primary master ntwk_1 ntwk_2 ntwk_1 fails ntw k_1 returns the dot means the a clock driving pll is synchronized to this reference clock switi_024.wmf ct_c8_b; ct_frame_b pef 20451 / 20471 / 24471 architectural description preliminary data sheet 40 2001-11-16 preliminary figure 16 clock fallback of secondary master the secondary master is synchronized to ct_c8_a, ct_frame_a and drives ct_c8_b and ct_frame_b . if one of the ct_a clocks fail the device may synchronize automatically or by software command (depends on configuration) to another reference clock (ntwk or ct_netref). figure 16 shows a configuration example. if not masked the failure is reported by interrupt. the reference and the fallback must be programmed again if the automatic fallback to the new reference was performed. any fallback and re-programming will be performed without data loss in the device. ct_netref_1 secondary master ntwk_1 ct_netref_2 ntwk_2 secondary master ntwk_1 ntwk_2 ct_c8_a fails the dot means the b clock driving pll is synchronized to this reference clock switi_025.wmf ct_c8_a; ct_frame_a ct_c8_b; ct_frame_b pef 20451 / 20471 / 24471 architectural description preliminary data sheet 41 2001-11-16 preliminary figure 17 clock fallback of slave the slave is synchronized to ct_c8_a and ct_frame_b . if the clock fails the slave synchronizes automatically or by software command to ct_c8_b and ct_frame_b . if not masked the failure is reported by interrupt. in the case of an automatic fallback to the ct_cb or ct_ca clocks the new reference must be programmed. the fallback and the re-programming of the source will be done without any data loss regarding the stratum 4e specification. additionally the fallback must be issued again if needed. ct_netref_1 slave ntwk_1 ct_netref_2 ntwk_2 slave ntwk_1 ntwk_2 ct_c8_a fails the dot means the internal clock pll is synchronized to this reference clock the square means the netref providing pll is synchronized to this reference clock switi_026.wmf ct_c8_a; ct_frame_a ct_c8_b; ct_frame_b pef 20451 / 20471 / 24471 architectural description preliminary data sheet 42 2001-11-16 preliminary 3.5 loops the loop command in the configuration command register cmd2 provides support for automatic pcm-pcm and h.1x0-h.1x0 loops. ? pcm-pcm loop all input lines are pad connected with the corresponding output line. h.1x0-h.1x0 loop the first 16 h-bus lines are pad connected with the corresponding upper 16 h-bus lines. e.g. h0 -> h16; h1 -> h17; ....... after the loop disable command was set the lines will be set in high-impedance after approximately two frames. 3.6 read switi configuration with indirect register addressing since the switi configuration can be programmed with defined instructions in the cmd1 and cmd2 registers it is possible to read the current configuration through the indirect access registers. the indirect addressing is started by writing one of the five read configuration commands in the cmd2 register. the five commands can be separated in two groups, internal configuration and external line configuration. the internal configuration, e.g. clock generator, ireq pin can be read with command "read configuration". the internal settings are decoded with the instruction bits i3..0. the data rate for the pcm and h.1x0 interface can be read with the "read pcm / h.1x0 line configuration" commands and to get the gpclk line configuration and the bit shift value the "read gpclk configuration" and "read bit/clock shift configuration" must be issued. the tsv and con registers contain the required information after the internal read process is complete. the recovery time is 240 ns. to read the correct configuration data from the tsv register it is not allowed to use the command "read time-slot value" before the tsv register has been read. pef 20451 / 20471 / 24471 architectural description preliminary data sheet 43 2001-11-16 preliminary 3.7 power-on and reset behavior 3.7.1 hardware reset there are three independent low active reset pins: reset , ct_reset and trst . if the reset or ct_reset (in conjunction with the mode pins m-mode and h.110 mode) pin is activated, it immediately places all outputs and i/o ports into tri-state, except the eclko pin. after the reset process the correct external frequency must be set with the command ? set external frequency ? accordingly. this command starts the configuration process for the apll. the apll is locked after 750 s. during this period the apll is bypassed and the internal frequency is 2.048 mhz. if the apll is locked the internal frequency will be 49.152 mhz. individual output sections must be enabled by setting the command in the configuration command register cmd1 , or cmd2 . internally all state machines, counters and registers are cleared and set to their defined reset value. the h.110 controller is in the reset state and all h.110 i/o pins are tri-stated as long as the ct_reset pin is asserted. (see ? ct_reset ? on page 48 ) the reset and ct_reset pins don ? t control the boundary scan register and tap- controller. if the trst pin is asserted the tap-controller will go into the test-logic-reset state and all boundary scan elements are bypassed. all outputs and i/o-pins are controlled by the core logic and are tristated according to the programmed functionality or the core reset condition (pin reset ). the hardware reset must be issued for a minimum of 1 s, for more details please refer to the chapter ? hardware reset timing ? on page 146 . 3.7.2 software reset the software reset is accomplished by setting the ? set software reset ? command in the cmd2 register. the software reset clears the complete device except the clocking unit and the temporary microprocessor registers (e.g. cmd1 ). the software reset can be deactivated with the ? set software reset ? command. during software reset the microprocessor interface doesn ? t accept any other commands for a minimum of 1 s. pef 20451 / 20471 / 24471 description of interfaces preliminary data sheet 44 2001-11-16 preliminary 4 description of interfaces 4.1 local bus interface (pcm) the local bus is a pcm interface consisting of input and output data lines (in, out), a pcm data clock pdc and a frame synchronization signal pfs. figure 18 pcm interface configurations the pfs frame sync is a 8 khz signal and delimiting the frame. this input signal is used by the switi to determine the start of a frame. a frame is divided into 8-bit wide time-slots. the amount of time-slots within a frame depends on the selected data rate of pdc which can be 2.048 mbit/s, 4.096 mbit/s, 8.192 mbit/s, 16.384 mbit/s. the pfs input has a schmitt-trigger characteristic. the pdc data clock input supply the switi with a data clock. it can be operated with 2.048 mhz, 4.096 mhz, 8.192 mhz, or 16.384 mhz data rate clock depending on the selected highest data mode. the pdc clock signal must be equal or higher as the highest data rate. the pdc input has a schmitt-trigger characteristic. a clock slave must receive pfs and pdc whereas a clock master drives these signals. to enable or disable the signals for the clock master the command ? pcm clock input/ output selection ? must be issued. the time-slots are transmitted and received via 16 input and 16 output lines ( in[15:0] , out[15:0] ) . the input lines have a schmitt-trigger characteristic. the output lines have tristate outputs with push-pull characteristic. for every time-slot not participating to a connection the output is high impedance. with the special command "local bus (pcm) standby" in the cmd2 register it is possible to set all pcm lines in a high impedance state during the normal operation mode. all pcm lines are in high impedance state after the reset process and must be enabled with the "local bus (pcm) standby" command. all lines which are not participating on a switching operation are in high impedance state and the time-slot information on the input lines are discarded automatically. pcm i/o pfs pdc in out pcm i/o pfs pdc in out clock slave clock master switi_037.wmf pef 20451 / 20471 / 24471 description of interfaces preliminary data sheet 45 2001-11-16 preliminary figure 19 pcm bit shifting for each pcm input line the offset of time-slot zero can be adjusted in a range from 0 to 7 bit in half clock resolution before or after the pfs rising edge. for all output lines the offset of time-slot zero can be adjusted in a range from 0 to 7 bit in half clock resolution after the pfs rising edge. the resolution depends on the selected data rate that means the resolution doesn ? t depend on the pdc signal. after the reset process the bit shift is disabled for all lines. that means the time-slot 0 starts with the rising edge of pfs. all input data will be sampled with falling edge of the selected data rate and the output data are valid with the rising edge of the selected data rate. pfs 01 0 77 data rate of the selected line input 0 o ffset of ts0 input 1 o ffset of ts0 outputs o ffset of ts0 switi_039.emf pef 20451 / 20471 / 24471 description of interfaces preliminary data sheet 46 2001-11-16 preliminary 4.2 h-bus interface figure 20 h-bus interface in h.100 mode htsi peb 2xxxx v ss v dd d[7:0] a[4:0] ds rd wr r/w ct_d[31:0] /ct_frame_a ct_c8_a ct_c8_b /ct_frame_b ct_netref(_1) /fr_c o m p sclk c2 /c16+ /c4 tdi tdo tck tms cs ire q in[15:0] out[15:0] pfs pdc ale mode trst gpio general purpose clocks /c16- ct_netref_2 /ct_e n /ct_r es et sclkx2* / sclk-d switi_002.wmf ire q reset misc. pef 20451 / 20471 / 24471 description of interfaces preliminary data sheet 47 2001-11-16 preliminary figure 21 h-bus interface in h.110 mode note: the frequency of sclk in h.110 mode is 8.192 mhz only. 4.2.1 ct_c8(a/b) and ct_frame(a/b) the functional timing relationship of the ct bus clocks can ct_frame can be found in the chapter ? h-bus and pcm (local bus) frame structure ? on page 132 . the ct_frame is a 8 khz signal and delimiting the frame. the negative pulse, nominally 122 ns wide marks the beginning of the first bit of the first time-slot. the ct_c8 is the 8.192 mhz bit clock. the duty cycle of this signal is nominally 50%. a h.1x0 slave must receive ct_c8 and ct_frame whereas a clock master drives these signals. 4.2.2 dataports there are 32 bidirectional pins available for accessing the h-bus. the frame structure is shown in chapter 7.3 . for every pin there is a tri-state controller. the ct_en signal enables the tri-state controller for the h.110 data lines. with the special command "pcm ct_frame_a: 8 khz; driven by master a ct_c8_a: 8.192 mhz; driven by master a; 50% duty cycle ct_frame_b: 8 khz; redundant; driven by master b ct_c8_b: 8.192 mhz; redundant; driven by master b; 50% duty cycle ct_d[31:0]: 4096 ts fr_comp: 8 khz; scbus (fsync*) sclk: 8.192 mhz; scbus core signals inter-operability with ansi vita 6 scbus sclk-d: 8.192 mhz; scbus ct_netref_1: 8 khz, 1.544 mhz, 2.048 mhz; any duty cycle ct_netref_2: 8 khz, 1.544 mhz, 2.048 mhz; any duty cycle c t_en : indication that j4 is fully seated ct_reset 32 switi_033.emf pef 20451 / 20471 / 24471 description of interfaces preliminary data sheet 48 2001-11-16 preliminary and h.1x0 standby" in the cmd2 register it is possible to set all h.1x0 lines in a high impedance state during the normal operation mode. all h.1x0 lines are in high impedance state after the reset process and must be enabled with the "pcm and h.1x0 standby" command. all lines which are not participating on a switching operation are in high impedance state. the default data rate is 8.192 mbit/s in accordance to the h.100/h.110 specification. with the configuration command register it is possible to select a individual data rate from 2.048 mbit/s, 4.096 mbit/s, and 8.192 mbit/s in accordance to support the interoperabilitiy busses. 4.2.3 c t_en the ct_en signal must be implemented in an identical manner to the implementation of the bd_sel# signal as specified in the picmg 2.1 compactpci hot swap specification by connecting ct_en to a logic high (de-asserted) through a 1.2k 5% resistor or current source equivalent. the ct_en signal indicates that a pci board is fully seated. the h.110 interface logic is enabled if the ct_en signal is active (logic low level enables all h.110 ports, pcm ports, and clock signals). 4.2.4 ct_reset the ct_reset must be functionality and electrically equivalent to the compactpci signal rst#. the device must respond to the ct_reset signal when it is asserted. all h.110 outputs and i/os are high impedance until the ct_reset is released as well as the related pcm outputs and i/os. no clocking signal can influence the internal logic during the reset state. all internal state machines and counters are in a defined reset state after the ct_reset signal is released and the connection memory is in the reset state. after the ct_reset signal is released the device has to be configured with the configuration command register 1 and 2 ( cmd1 , cmd2 ). the reset and ct_reset (in conjunction with the mode pins m-mode and h.110 mode) signals are logical or connected. 4.2.5 h-mvip c 16 signals the differential signal is driven by the clock master and used to read and write bits on the serial data lines. time-slot boundaries align with the falling edge of c16+ . the c16 signal is differential. the switi doesn ? t have a integrated differential receiver/ transceiver with the required thresholds of the eia standard rs-485. nevertheless the differential c16+ , c16- input signals are logical decoded to one internal /c16 signal if the switi is configured as clock slave. the c16- is the inverted c 16+ signal if the switi shall generate the c16+ , c16- signals. pef 20451 / 20471 / 24471 description of interfaces preliminary data sheet 49 2001-11-16 preliminary 4.3 data rate the switi provides the programming of data rates on a per line basis for the local bus as well as for the h.100/h.110 bus. to support the h.100/h.110 bus and the interoperability bus systems all 32 h.100/h.110 data lines can operate with 2.048 mhz, 4.096 mhz, and 8.192 mhz independently. the following table shows the possible data rates for the different lines. all local bus lines can operate with 2.048 mhz, 4.096 mhz, and 8.192 mhz independently and up to 24 local bus lines for the htsi in m-mode or 8 local bus lines for the htsi in h-mode can operate with 16.384 mhz as well. having 16.384 mbit/s in any of the pcm0..7 lines, the corresponding (pcm0..7 + 8) lines will be deactivated (tri- state). using all pcm0...7 lines with 16.384 mbit/s all the pcm8...15 will be then deactivated. the input and output lines are independent of each other, i.e. for a given bus line the input and the output lines can be programmed with different data rates. for the htsi the maximum aggregate data rate supported at the input and output bus lines is 393.216 mbit/s, (e.g. 24 lines x 16.384 mbit/s per line = 393.216 mbit/s, as input and/or output). the following tables show some possible configurations for the local and h-bus lines, with the highest data rate allowed. note: table 12 and table 13 show all possibile combinations with only 8.192 mbit/s and/or 16.384 mbit/s for all available bus lines table 11 data rates for local and h-bus pcm0..7 (in/out) pcm8..15 (in/out) pcm16..31 (in/out) h0..31 htsi-m 2/4/8/16 mbit/s 2/4/8 mbit/s 2/4/8/16 mbit/s x htsi-h 2/4/8/16 mbit/s 2/4/8 mbit/s x 2/4/8 mbit/s table 12 maximum possible data rates for htsi in m-mode pcm0..7 (in/out) pcm8..15 (in/out) pcm16..31 (in/out) h0..31 8 x 16.384 mbit/s x 16 x 16.384 mbit/s x 8 x 16.384 mbit/s x 16 x 8.192 mbit/s x 8 x 8.192 mbit/s 8 x 8.192 mbit/s 16 x 16.384 mbit/s x 8 x 8.192 mbit/s 8 x 8.192 mbit/s 16 x 8.192 mbit/s x table 13 maximum possible data rates for htsi in h-mode pcm0..7 (in/out) pcm8..15 (in/out) pcm16..31 (in/out) h0..31 8 x 16.384 mbit/s x x 32 x 8.192 mbit/s 8 x 8.192 mbit/s 8 x 8.192 mbit/s x 32 x 8.192 mbit/s pef 20451 / 20471 / 24471 description of interfaces preliminary data sheet 50 2001-11-16 preliminary 4.4 microprocessor interface a standard 8-bit multiplexed or non-multiplexed p interface is provided, compatible to intel/siemens (e.g. 80386ex, c166) and motorola (e.g. 68040, 68340, 68360, 801) bus systems. if the gpio port is not needed it can be used to provide a 16-bit p interface. the 16-bit mode is determined according to mode16 input pin. mode16 = ? 0 ? -> 8-bit interface mode16 = ? 1 ? -> 16-bit interface this chapter describes how to configure the p interface to each mode. 4.4.1 intel/siemens or motorola mode the intel/siemens or motorola mode for the p interface can be configured during the hardware reset process in conjunction with the ale pin. ? ale permanently driven to ? low ? => motorola mode ? ale permanently driven to ? high ? => intel/siemens mode ? edge on ale => intel/siemens multiplexed mode a falling or rising edge on ale during the normal operation selects the multiplexed mode immediately. with the hardware reset and the tied ale pin it is possible to return to the motorola or intel/siemens mode. 4.4.2 de-multiplexed or multiplexed mode in both modes, the a-bus and the d-bus are used in parallel. the a-bus should be connected to the lsbs of ad-bus, coming from the p, also in multiplexed mode. the next figure describes the connection to the address and data buses in the different modes. note: motorola mode is used only with de-multiplexed ad bus. intel/siemens mode may be used with both, multiplexed or de-multiplexed ad bus. pef 20451 / 20471 / 24471 description of interfaces preliminary data sheet 51 2001-11-16 preliminary figure 22 multiplexed and in de-multiplexed bus mode note: in both modes only the 5 lsbs of a-bus or ad/bus are connected to the address inputs. multiplexed mode p switi ad d a ale ale latch de-multiplexed mode p switi d d a ale latch ?1? a 8/16 5 8/16 5 pef 20451 / 20471 / 24471 description of interfaces preliminary data sheet 52 2001-11-16 preliminary 4.5 general purpose port (gpio) this port consists of 8 lines each one configurable as input or output. a change on an input line may cause an interrupt (if not masked). the user has access to the port configuration and information via the appropriate registers of the p interface. figure 23 shows an example. figure 23 gpio port configuration example 1 0 1 0 x x x x x x x x 1 1 0 0 1 1 1 1 0 0 0 0 70 1 changes in line 1 or line 0 cause interrupts gpio pin no. signal 1 0 1 0 1 1 1 x x x x 0 0 1 0 x x x x 1 1 0 1 x = don't care contains current value of input lines change on input line 1 detected line 7 to 4 as outputs line 3 to 0 as inputs switi_055.emf 2 3 4 5 6 gpio output register gpio mask register gpio direction register gpio input register gpio interrupt register drive 1010 on lines [7:4] 1->0 pef 20451 / 20471 / 24471 description of interfaces preliminary data sheet 53 2001-11-16 preliminary 4.6 general purpose clocks the switi provides 8 general purpose clock lines. with two independent commands in the cmd2 register the lines can be configured as frame group signals or individual clock signals. the last written command for a line is valid and controls the multiplexer. 4.6.1 frame group outputs via 8 output lines it is possible to provide 8 different framing signals which are used for synchronization purpose. all signals have a period of 125 s. their offset can be programmed individually within the pfs determined frame in a resolution of 61 ns (1/ 16.384 mhz). the default start point for the offset is the beginning of a frame (rising edge of pfs and the clock signal). the start point for the offset can be shifted for a half clock cycle, that means the second start point is determined with the rising edge of pfs and the next falling edge of the clock signal (as shown in figure 24). the high time of the signal can also be programmed in steps of 61 ns. all frame signals can be controlled as high or low active. figure 24 frame signal example figure 24 shows an example of a frame signal beginning with the rising edge of the 64th clock cycle with a length of 4 clock cycles. further programming examples can be found 4.6.2 gpclk as clock outputs all 8 gpclk lines can be configured as individual clock outputs with 8 khz, 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz and for test purposes with the internal frequency or the input frequency of the analog pll (apll). all clock signals are generated from the analog pll output frequency which is the internal frequency. the quality of all output frequency signals depends on the quality of the selected input pll frequency. pfs 125s 16.384 mbit/s 01 frame signal 125s 64 switi_038.emf pef 20451 / 20471 / 24471 description of interfaces preliminary data sheet 54 2001-11-16 preliminary 4.7 jtag (boundary scan) the switi provides a fully ieee 1149.1 compatible boundary scan support consisting of: ? a complete boundary scan chain ? a test access port controller (tap controller) ? five dedicated pins: tck, tms, tdi, tdo and a trst to asynchronously reset the tap controller ? one 32-bit idcode register 4.7.1 boundary scan all pins except power supply and crystal are included in the boundary scan. depending on the pin functionality one (input), two (output, enable) or three (input, output, enable) boundary scan cells are provided. the maximum clock rate at pin tck is 10 mhz. 4.7.2 test-access-port (tap) the following signal pins allow the boundary scan test logic to be accessed: ? tck ? test clock input to which a central bsc test clock is applied. this bsc test clock is independent of the system clock. clock phases are derived from this clock for test sequence control. ? tms ? test mode select control input for which the desired status changes at the tap controller by applying a certain level (0/1) caused by the rising edge of tck. ? tdi ? test data input whose data is inserted into the test logic with the rising edge of the tck. ? tdo ? test data output with tristate capability which is only active during the shift-ir and shift-dr controller state, and whose data is driven with the falling edge of tck. pef 20451 / 20471 / 24471 description of interfaces preliminary data sheet 55 2001-11-16 preliminary 4.7.3 tap controller the test access port (tap) controller implements the state machine defined in the jtag standard ieee 1149.1. transitions on the pin tms cause the tap controller to perform a state change. the possible instructions are listed in the following table. the instruction length is four bit. extest is used to verify the board interconnections. when the tap controller is in the state ? update dr ? , all output pins are updated with the falling edge of tck. when it has entered state ? capture dr ? the levels of all input pins are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. intest supports internal chip testing. when the tap controller is in the state ? update dr ? , all inputs are updated internally with the falling edge of tck. when it has entered state ? capture dr ? the levels of all outputs are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. sample/preload the sample/preload instruction enables all signal pins (inputs and outputs) to be sampled during operation (sample) and the result to be shifted out through the shift bsc register. the function of the internal logic is not influenced by this instruction. while shifting out, the bsc cells can be serially loaded at the same time with defined values through tdi (preload). the sample/preload instruction selects the boundary scan register in normal mode. in state capture-dr data is loaded into the boundary scan register with the rising edge of tck. in state update-dr the contents of the boundary scan register are written into the second register stage of the boundary scan register. this data becomes effective at the outputs only if an instruction has been activated that sets the bsc register to test mode: e.g. extest or clamp. table 14 tap controller instructions code instruction function 0000 extest external testing 0001 idcode reading id code 0100 highz high impedance state of all boundary scan outputs 0101 sample/preload snap-shot testing 0110 intest internal testing 0111 clamp reading outputs 1111 bypass bypass operation pef 20451 / 20471 / 24471 description of interfaces preliminary data sheet 56 2001-11-16 preliminary idcode the 32-bit identification register is serially read out via tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). the lsb is fixed to ? 1 ? .. clamp the bsc register is in test mode. for the duration of the clamp instruction, the bypass register is selected so that a minimal shift path is created. during shift-dr data can be shifted through the bypass register. the contents of the bsc register does not change during the update-dr state. highz the highz instruction disables all outputs if switched to high impedance state. the outputs are switched to high impedance in state update-ir. the outputs are redefined according to the next new instruction if another instruction has become active with update-ir. the selected test data register is the bypass register. bypass , a bit entering tdi is shifted to tdo after one tck clock cycle, e.g. to skip testing of selected ics on a printed circuit board. version device code manufacturer code output xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx 1 --> tdo table 15 boundary scan idcode version device code manufacture code bit0 htsi 0010 0000 0000 0110 1101 0000 1000 001 1 htsi-l 0010 0000 0000 0110 1110 0000 1000 001 1 htsi-xl 0010 0000 0000 0110 1111 0000 1000 001 1 pef 20451 / 20471 / 24471 description of interfaces preliminary data sheet 57 2001-11-16 preliminary 4.8 identification code via p read access the switi offers two possibilities to read the identification code. ? via the jtag port as described in chapter 4.7 ? or via the processor interface after a hardware reset the identification code is stored in the general purpose interrupt register ( gpi ) and can be read via the processor interface. the high nibble is the version number and the low nibble is equal to the low nibble of the device code shown in table 16 . for the 8-bit p interface configuration the first write access to the general purpose mask register ( gpm ) will reset the register gpi to 00 h . if the p interface is configured as a 16-bit interface the idcode can always be read from the gpi register, that means the gpi register will not be reset. the idcode for the p read access is shown in table 16 . note: the version number of the idcode register remains unchanged. table 16 idcode via p read access 8-bit idcode (msb..lsb) version device code htsi 0010 1101 htsi-l 0010 1110 htsi-xl 0010 1111 pef 20451 / 20471 / 24471 register description preliminary data sheet 58 2001-11-16 preliminary 5 register description the register description gives information about all registers accessible via the microprocessor interface according to address, short name, access, reset value and value range. pef 20451 / 20471 / 24471 register description preliminary data sheet 59 2001-11-16 preliminary 5.1 register overview for 8-bit interface table 17 register overview for 8-bit interface reg name access 8-bit address reset value comment page no. spa rd/wr 00 h 00 h source port address register value range see table 18 61 itsa rd/wr 01 h 00 h input time-slot address register value range see table 19 61 dpa rd/wr 02 h 00 h destination port address register value range see table 18 62 otsa rd/wr 03 h 00 h output time-slot address register value range see table 19 62 sca rd/wr 07 h 00 h subchannel address register value range see table 20 62 gi1 rd/wr 04 h 00 h general input register 1 63 gi2 rd/wr 05 h 00 h general input register 2 65 ccmd rd/wr 06 h 00 h connection command register 66 cmd1 rd/wr 08 h 00 h configuration command register 1 68 cmd2 rd/wr 0a h 00 h configuration command register 2 74 mv rd/wr 0c h 00 h message value register 78 ista1 rd 0e h 00 h interrupt status register 1 78 iesta1 rd 10 h 00 h interrupt error status register 1 79 iesta2 rd 11 h 00 h interrupt error status register 2 80 intm1 rd/wr 12 h 3d h interrupt mask register 1 81 intem1 rd/wr 14 h 3f h interrupt error mask register 1 82 intem2 rd/wr 15 h ff h interrupt error mask register 2 83 gppi rd 16 h 00 h general purpose port input register 83 gppo wr 18 h 00 h general purpose port output register 84 gpd rd/wr 1a h 00 h general purpose direction register 84 gpm rd/wr 1b h ff h general purpose mask register 84 gpi rd 1c h idcode general purpose interrupt register 85 tsv rd 1e h xx h time-slot value register 85 con rd 1f h xx h configuration register 89 pef 20451 / 20471 / 24471 register description preliminary data sheet 60 2001-11-16 preliminary table 18 value range for spa/dpa addressed lines value range bit4..0 local-bus input lines (h-mode) 15..0 local-bus input lines (m-mode) 31..0 h-bus lines (h-mode) 31..0 table 19 value range for itsa/otsa data rate range bit7..0 2.048 mbit/s 31..0 4.096 mbit/s 63..0 8.192 mbit/s 127..0 16.384 mbit/s 255..0 table 20 value range for sca mode range 1-bit switching 0..7 for isca0..2; 0..7 for osca0..2 2-bit switching 0..3 for isca0..1; 0..3 for osca0..1 4-bit switching 0..1 for isca0; 0..1 for osca0 pef 20451 / 20471 / 24471 register description preliminary data sheet 61 2001-11-16 preliminary 5.2 detailed register description for 8-bit interface source port address register rd/wr address: 00 h reset value: 00h input time-slot address register rd/wr address: 01 h reset value: 00h 76543210 spa bt 0 0 pa4 pa3 pa2 pa1 pa0 bt bus type (must be set to logical "0" in m-mode) 0 = local bus 1 = h-bus pa4..0 port address 76543210 itsa tsa7 tsa6 tsa5 tsa4 tsa3 tsa2 tsa1 tsa0 tsa7..0 time-slot address pef 20451 / 20471 / 24471 register description preliminary data sheet 62 2001-11-16 preliminary destination port address register rd/wr address: 02 h reset value: 00h output time-slot address register rd/wr address: 03 h reset value: 00h subchannel address register rd/wr address: 07 h reset value: 00h 76543210 dpa bt 0 0 pa4 pa3 pa2 pa1 pa0 bt bus type (must be set to logical "0" in m-mode) 0 = local bus 1 = h-bus pa4..0 port address 76543210 otsa tsa7 tsa6 tsa5 tsa4 tsa3 tsa2 tsa1 tsa0 tsa7..0 time-slot address 76543210 sca 0 0 osca2 osca1 osca0 isca2 isca1 isca0 osca2..0 output subchannel address isca2..0 input subchannel address pef 20451 / 20471 / 24471 register description preliminary data sheet 63 2001-11-16 preliminary general input register 1 rd/wr address: 04 h reset value: 00h in case of a pll reference (main and secondary) selection command (cmd1) the content of this register is interpreted as follows: in case of a ct_netref_1/2 output selection command (cmd1) the content of this register is interpreted as follows: 76543210 gi1 gv7 gv6 gv5 gv4 gv3 gv2 gv1 gv0 gv7..0 general value gv2..0 clock frequency 000 = 8 khz 001 = 512 khz 010 = 1.536 mhz 011 = 1.544 mhz 100 = 2.048 mhz 101 = 4.096 mhz 110 = 8.192 mhz 111 = 16.384 mhz gv1..0 output ct_netref_1/2 clock frequency 00 = 8 khz 01 = 512 khz 10 = 2.048 mhz pef 20451 / 20471 / 24471 register description preliminary data sheet 64 2001-11-16 preliminary in case of a bit shift command (cmd1) the content of this register is interpreted as follows: in case of the gpclk as frame signal command (cmd2) the content of this register is interpreted as follows: in case of the gpclk as clock signal command (cmd2) the content of this register is interpreted as follows: gv4 bit shift value (only for input lines) 0 = bit shift applies before pfs rising edge 1 = bit shift applies after pfs rising edge gv3..1 bit shift value (range: 7 to 0) gv0 edge control bit (half clock shift) 0 = data transmit with rising edge and is sampled with falling edge 1 = data transmit with falling edge and is sampled with rising edge gv7..2 offset within the pfs frame in number of 16.384 mhz clock cycles (lower 6 bits; refer to gi2 for the upper part) gv1 edge control bit 0 = data changes with rising edge and is sampled with falling edge 1 = data changes with falling edge and is sampled with rising edge gv0 reserved gv2..0 output frequency for the selected line 000 = 8 khz 001 = 2.048 mhz 010 = 4.096 mhz 011 = 8.192 mhz 100 = 16.384 mhz 101 = input analog pll (2.048 mhz) 110 = internal frequency (49.152 mhz) pef 20451 / 20471 / 24471 register description preliminary data sheet 65 2001-11-16 preliminary general input register 2 rd/wr address: 05 h reset value: 00h in case of the gpclk as frame signal command (cmd2) the content of this register is interpreted as follows: 76543210 gi2 gv7 gv6 gv5 gv4 gv3 gv2 gv1 gv0 gv7..0 general value gv7..5 width of the pulse in number of 16.384 mhz clock cycles from 1 to 8 i.e. gv7..5 = 000 => 1 clock cycle, gv7..5 = 010 => 3 clock cycles gv4..0 offset within the pfs frame in number of 16.384 mhz clock cycles (upper 5 bits; refer to gi1 for the lower part) pef 20451 / 20471 / 24471 register description preliminary data sheet 66 2001-11-16 preliminary connection command register rd/wr address: 06 h reset value: 00 h 76543210 ccmd i3 i2 i1 i0 cc3 cc2 cc1 cc0 cc3..0 command code 0000 = no operation at all 0001 = constant delay connection command (incl. broadcast connection) (spa, itsa, dpa, otsa, sca are considered) i1..0 subchannel mode 00 = 8-bit wide time-slots 01 = 4-bit wide time-slots 10 = 2-bit wide time-slots 11 = 1-bit wide time-slots 0010 = minimum delay connection command (incl. broadcast connection) (spa, itsa, dpa, otsa are considered) 0011 = send message command (always constant delay) (dpa, otsa, mv are considered) 0100 = stop message command (dpa, otsa are considered) 0101 = disconnect command (spa, itsa, dpa, otsa, sca are considered) i1..0 see i1..0 of constant delay connection command (incl. broadcast connection) 0110 = disconnect part of broadcast command (spa, itsa, dpa, otsa, sca are considered) i1..0 see i1..0 of constant delay connection command (incl. broadcast connection) 0111 = multipoint connect command (spa, itsa, dpa, otsa are considered) i0 multipoint mode 0 = logical or connection 1 = logical and connection pef 20451 / 20471 / 24471 register description preliminary data sheet 67 2001-11-16 preliminary 1000 = disconnect all command 1001 = bidirectional connect command (spa, itsa, dpa, otsa are considered) i0 delay mode 0 = minimum delay 1 = constant delay 1010 = memory dump (connection and data memory) i0 memory dump 0 = disable 1 = enable pef 20451 / 20471 / 24471 register description preliminary data sheet 68 2001-11-16 preliminary configuration command register 1 rd/wr address: 08 h reset value: 00h 76543210 cmd1 i3 i2 i1 i0 cc3 cc2 cc1 cc0 cc3..0 command code 0000 = no operation 0001 = set as h.100/h.110 master/slave (htsi h-mode) must be programmed only after pll input initialization and/or h.1x0 fallback command i0 mode information 0 = slave mode 1 = master mode 0010 = pll primary reference selection command for master (gi1 is considered to set the frequency) i3..0 synchronization information 0000 = no synchronization = internal oscillator (default) 0001 = synchronizes the pll to pfs (only m-mode) 0010 = synchronizes the pll to pdc (only m-mode) 0011 = synchronizes the pll to ct_netref_1 (only h- mode) 0100 = synchronizes the pll to ct_netref_2 (only h- mode) 0101 = synchronizes the pll to ntwk_1 0110 = synchronizes the pll to ntwk_2 0111 = synchronizes the pll to ct_a (ct_c8_a and ct_frame_a ) (only h-mode, gi1 isn ? t considered) 1000 = synchronizes the pll to ct_b (ct_c8_b and ct_frame_b ) (only h-mode, gi1 isn ? t considered) 1001 = not used 1010 = not used 1011 = synchronizes the pll to fr_comp (only h-mode) 1100 = synchronizes the pll to sclk (only h-mode) pef 20451 / 20471 / 24471 register description preliminary data sheet 69 2001-11-16 preliminary 1101 = synchronizes the pll to c2 (only h-mode) 1110 = synchronizes the pll to c4 (only h-mode) 1111 = synchronizes the pll to c16 (only h-mode) 0011 = pll secondary reference selection command for master (only h- mode) (gi1 is considered to set the frequency) i3..0 synchronization information 0000 = no synchronization = internal oscillator (default) 0001 = synchronizes the pll to ct_netref_1 0010 = synchronizes the pll to ct_netref_2 0011 = synchronizes the pll to ntwk_1 0100 = synchronizes the pll to ntwk_2 0101 = synchronizes the pll to ct_c8_a 0110 = synchronizes the pll to ct_c8_b 0111 = synchronizes the pll to ct_frame_a 1000 = synchronizes the pll to ct_frame_b 1001 = synchronizes the pll to fr_comp 1010 = synchronizes the pll to sclk 1011 = synchronizes the pll to sclkx2 1100 = synchronizes the pll to c2 1101 = synchronizes the pll to c4 1110 = synchronizes the pll to c16 1111= start special configuration register programming 0100 = pll source selection command. - slave path (only h-mode) i3..0 source/frequency information 0000 = not used 0001 not used 0010 not used 0011 not used 0100 not used 0101 ct_a (ct_c8_a and ct_frame_a ) 0110 ct_b (ct_c8_b and ct_frame_b ) 0111 sclk = 2.048 mhz and f r_comp pef 20451 / 20471 / 24471 register description preliminary data sheet 70 2001-11-16 preliminary 1000 sclk = 4.096 mhz and fr_comp 1001 sclk = 8.192 mhz and fr_comp 1010 c2 = 2.048 mhz and fr_comp 1011 c4 = 4.096 mhz and fr_comp 1100 c 16 = 16.384 mhz and fr_comp 1111 write special configuration register (gi1 is considered) 0101 = h.100/h.110 clock output selection command (only h-mode) i1..0 activation information 00 = disable ct_frame and ct_c8 (default) 01 = enable c t_frame_a and ct_c8_a 10 = enable ct_frame_b and ct_c8_b i3..2 not used must be set to ? 0 ? 0110 = pcm clock input/output selection command (default: pfs and pdc inactive) i2..0 frequency information 000 = reserved 001 = enable pfs and pdc = 2.048 mhz 010 = enable pfs and pdc = 4.096 mhz 011 = enable pfs and pdc = 8.192 mhz 100 = enable pfs and pdc = 16.384 mhz i3 direction information 0 = pfs and pdc as input 1 = pfs and pdc as output 0111 = compatibility clock output selection command (only h-mode) i0 mvip-90 activation information 0 = disable mvip-90 - c2, c4 , fr_comp (default) 1 = enable mvip-90 - c2, c4 , fr_comp i1 h-mvip activation information 0 = disable h-mvip - c2, c4 , c16 , fr_comp (default) 1 = enable h-mvip - c2, c4 , c 16 , fr_comp i3..2 scbus activation/frequency information 00 = disable scbus - sclk, sclkx2, fsync* (default) pef 20451 / 20471 / 24471 register description preliminary data sheet 71 2001-11-16 preliminary 01 = enable scbus - 2.048 mhz 10 = enable scbus - 4.096 mhz 11 = enable scbus - 8.192 mhz 1000 = ct_netref_1 output selection command (only h-mode) i0 inversion information 0 = normal ct_netref_1 output 1 = invert ct_netref_1 output i3..1 activation information 000 = disable ct_netref_1 (default) 001 = enable ct_netref_1 - source ntwk_1 010 = enable ct_netref_1 - source ntwk_2 011 = enable ct_netref_1 - source netref_2 100 = enable ct_netref_1 - source internal oscillator (gi1 is considered to set the output frequency) 1001 = ct_netref_2 output selection command (only h-mode) i0 inversion information 0 = normal ct_netref_2 output 1 = invert ct_netref_2 output i3..1 activation information 000 = disable ct_netref_2 (default) 001 = enable ct_netref_2 - source ntwk_1 010 = enable ct_netref_2 - source ntwk_2 011 = enable ct_netref_2 - source netref_1 100 = enable ct_netref_2 - source internal oscillator (gi1 is considered to set the output frequency) 1010 = h.100/h.110 fallback mechanism i1..0 pll source (only h-mode) 00 = disable (default) 01 = from pll main ref. to secondary ref. (if switi is primary "a" master in the system) 10 = from pll main ref. to secondary ref. (if switi is secondary "b" master in the system) 11 = from a clock to b clock (slave) pef 20451 / 20471 / 24471 register description preliminary data sheet 72 2001-11-16 preliminary i2 re-fallback activation information for primary master (only h-mode) 0 = disable automatic switch back to main ref. (default) 1 = enable automatic switch back to main ref. i3 pll phase alignment (please see description, chapter 3.4.4 ) 0 = disable (default after reset) 1 = enable must be set for h.1x0 slave 1011 = set bit rate command local bus (default for all lines = 2.048 mbit/s) i1..0 base bit rate information 00 = 2.048 mbit/s 01 = 4.096 mbit/s 10 = 8.192 mbit/s 11 = 16.384 mbit/s i2 destination information 0 = no effect 1 = set rate of local input lines (spa is considered) i3 destination information 0 = no effect 1 = set rate of local output lines (dpa is considered) 1100 = set bit rate command h.100/h.110 and interoperability bussystems (default for all lines = 2.048 mbit/s) i1..0 base bit rate information 00 = 2.048 mbit/s (spa is considered) 01 = 4.096 mbit/s (spa is considered) 10 = 8.192 mbit/s (spa is considered) 11 = set all lines to 8.192 mbit/s 1101 = read time-slot command i0 destination information 0 = read input time-slots(spa, itsa are considered) 1 = read output time-slots(dpa, otsa are considered) pef 20451 / 20471 / 24471 register description preliminary data sheet 73 2001-11-16 preliminary 1110 = stream to stream switch command (spa, dpa are considered) (the value for spa and dpa can not be equal) the command affects h-bus only and depends on the selected bit rate i1..0 connection (see figure 10 on page 28 ) depends on the selected bit for every line 00 = mode 0 01 = mode 1 10 = mode 2 11 = mode 3 i2 connection information 0 = release current stream to stream connection 1 = establish current stream to stream connection i3 destination information 0 = reserved 1 = release all programmed stream to stream connections 1111 = bit shift command (gi1 is considered to set shift value) (default: bit shift is inactive) i1..0 direction control 00 = set shift value for input line (spa is considered) 01 = set shift value for all input lines 10 = set shift value for all output lines 11 = set shift value for all lines (input and output) pef 20451 / 20471 / 24471 register description preliminary data sheet 74 2001-11-16 preliminary configuration command register 2 rd/wr address: 0a h reset value: 00h 76543210 cmd2 i3 i2 i1 i0 cc3 cc2 cc1 cc0 cc3..0 command code 0000 = no operation at all 0001 = external frequency i0 set external frequency (must be programmed first) 0 = 32.768 mhz 1 = 16.384 mhz i1 fallback to oscillator 0 = disable (and turn off ? enable ? status temporarily if fallback has occurred) 1 = enable if "fallback to oscillator" is enabled and a fallback has occurred, the corresponding failure is indicated in the iesta1 and/or iesta2 registers. for all clock failures, the pll bit ("pll source failure indication", iesta2 register) as well as the clock source related bit (in iesta1 or iesta2 register) will be set to "1". with the clock valid again the previously changed bits in iesta1 and/or iesta2 are set back to "0", the fallback must be disabled (cmd2=01 h /11 h ) for a few cycles and enabled again thereafter. i2 apll s parameters 0 = default 1 = start apll with improved parameters the command cmd2=41 h or cmd2=51 h to start the apll with improved parameters must only be issued only once after power up 0010 = parallel mode (local bus only) set the first 8 local bus input lines as 8 parallel input lines and set the first 8 local bus output lines as 8 parallel output lines. i0 set parallel mode pef 20451 / 20471 / 24471 register description preliminary data sheet 75 2001-11-16 preliminary 0 = disable 1 = enable 0011 = ireq pin command i1..0 set ireq pin (default: ireq is inactive) 00 = ireq is active low 01 = ireq is active high 10 = ireq as open-drain pin i2 set interrupt time-out counter set the inactive time between two consecutive interrupts 0 = disable = 20 ns 1 = enable = 300 ns 0100 = pcm and h.1x0 standby command i0 set pcm to high impedance 0 = outputs are tristated (default) 1 = outputs are enabled i1 set h.1x0 to high impedance (only h-mode) 0 = i/o ? s are tristated (default) 1 = i/os are enabled i2 not used must be set to ? 0 ? i3 internal pcm clock synchronization 0 = must be set in pcm clock master mode 1 = must be set in pcm clock slave mode 0101 = loop command i0 set pcm-pcm loop 0 = disable (default) 1 = enable i1 set h.100/h.110 loop (only h-mode) 0 = disable (default) 1 = enable 0110 = gpclk as frame signal command (gi1, gi2 are considered) (default: all gpclk ? s are tristated) i2..0 gpclk line (7..0) pef 20451 / 20471 / 24471 register description preliminary data sheet 76 2001-11-16 preliminary i3 invert mode 0 = frame signal is high active 1 = frame signal is low active 0111 = gpclk as clock signal command (gi1 is considered to set the frequency) (default: all gpclk ? s are tristated) i2..0 gpclk line (7..0) 1000 = set range of data rate command to avoid loss of data this command should be issued only once after reset. if the range of data rate is changed later on, loss of data must be expected for up to four frames. (additionally for the h-mode the 8.192 mbit/s bit must be set.) i3..0 range select to specify the range the min and max codes have to be logical or combined. 0001 = 2.048 mbit/s (default) 0010 = 4.096 mbit/s 0100 = 8.192 mbit/s 1000 = 16.384 mbit/s 1001 = read configuration i3..0 select configuration command 0000 = master/slave configuration (only h-mode) 0001 = pll primary master source 0010 = pll secondary master source (only h-mode) 0011 = pll source (slave path) (only h-mode) 0100 = clock output selection for h.1x0 (only h-mode) 0101 = clock output selection for pcm 0110 = clock output selection for interoperability signals (only h-mode) 0111 = output selection for ct_netref_1 (only h-mode) 1000 = output selection for ct_netref_2 (only h-mode) 1001 = fallback mechanism and phase alignment 1010 = external input frequency 1011 = parallel mode pef 20451 / 20471 / 24471 register description preliminary data sheet 77 2001-11-16 preliminary 1100 = ireq pin 1101 = h.1x0/pcm standby 1110 = loop 1111 = range of data rate 1010 = read gpclk configuration i2..0 gpclk line 7..0 1011 = read pcm line configuration i0 destination information 0 = read data rate of input line (spa is considered) 1 = read data rate of output line (dpa is considered) 1100 = read h.1x0 line configuration (spa is considered) (only h-mode) 1101 = read bit shift configuration i0 destination information 0 = shift value for input line (spa is considered) 1 = shift value for all output lines 1110 = reserved 1111 = software reset i0 set software reset 0 = deactivate software reset (default) 1 = activate software reset pef 20451 / 20471 / 24471 register description preliminary data sheet 78 2001-11-16 preliminary message value register rd/wr address: 0c h reset value: 00h interrupt status register 1 rd address: 0e h reset value: 00h 76543210 mv mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 mv7..0 message value 76543210 ista1 apll str er2 er1 gpio tsa nfc rdy apll apll lock indication 0 = pll is not locked = bypassed 1 = pll is locked str stream to stream indication 0 = no stream to stream connection is set 1 = stream to stream connections are set er2 error2 interrupt change indication (not active in 16-bit mode) 0 = no change detected in the interrupt error status register 2 (iesta2) 1 = change detected in the interrupt error status register 2 (iesta2) er1 error1 interrupt change indication 0 = no change detected in the interrupt error status register 1 (iesta1) 1 = change detected in the interrupt error status register 1 (iesta1) gpio general purpose change indication 0 = no change according to gp port inputs detected 1 = at least one change according to gp port inputs detected tsa time-slot arrived indication 0 = there is no new time-slot value in the register tsv pef 20451 / 20471 / 24471 register description preliminary data sheet 79 2001-11-16 preliminary interrupt error status register 1 rd address: 10 h reset value: 00h for all these status bits the values can be 1 = there is a new time-slot value in the register tsv nfc no further connections indication 0 = establishing of connections is possible 1 = the maximum amount of connections is reached rdy ready indication 0 = ccmd is not ready to be written to 1 = ccmd is ready to be written to 76543210 iesta1 0 0 nr2 nr1 ctb cta nw2 nw1 nr2 ct_netref_2 failure indication nr1 ct_netref_1 failure indication ctb ct_c8_b or ct_frame_b failure indication cta ct_c8_a or ct_frame_a failure indication nw2 ntwk_2 failure indication nw1 ntwk_1 failure indication 0 = no failure detected 1 = failure detected pef 20451 / 20471 / 24471 register description preliminary data sheet 80 2001-11-16 preliminary interrupt error status register 2 rd address: 11 h reset value: 00h for all these status bits the values can be 76543210 iesta2 con pll frc sc2 sc c2 c4 c16/s con connection memory error/overflow indication pll pll source failure indication frc fr_comp failure indication sc2 sclk2 failure indication sc sclk failure indication c2 c2 failure indication c4 c4 failure indication c16/s c16 failure indication c16/s secondary reference failure indication (only in master mode) 0 = no failure detected 1 = failure detected pef 20451 / 20471 / 24471 register description preliminary data sheet 81 2001-11-16 preliminary interrupt mask register 1 rd/wr address: 12 h reset value: 3dh mask = disable the interrupt 76543210 intm1 0 0 er2 er1 gpio tsa 0 rdy er2 error2 interrupt change indication mask (not active in 16-bit mode) 0 = do not mask the change indication bit 1 = mask the change indication bit er1 error1 interrupt change indication mask 0 = do not mask the change indication bit 1 = mask the change indication bit gpio general purpose change indication mask 0 = do not mask the change indication bit 1 = mask the change indication bit tsa time-slot arrived indication mask 0 = do not mask the time-slot arrived indication bit 1 = mask the time-slot arrived indication bit rdy ready indication mask 0 = do not mask the ready indication bit 1 = mask the ready indication bit pef 20451 / 20471 / 24471 register description preliminary data sheet 82 2001-11-16 preliminary interrupt error mask register 1 rd/wr address: 14 h reset value: 3fh for all these status bits the values can be mask = disable the interrupt 76543210 intem1 0 0 nr2 nr1 ctb cta nw2 nw1 nr2 ct_netref_2 failure indication mask nr1 ct_netref_1 failure indication mask ctb ct_c8_b or ct_frame_b failure indication mask cta ct_c8_a or ct_frame_a failure indication mask nw2 ntwk_2 failure indication mask nw1 ntwk_1 failure indication mask 0 = do not mask this interrupt 1 = mask this interrupt pef 20451 / 20471 / 24471 register description preliminary data sheet 83 2001-11-16 preliminary interrupt error mask register 2 rd/wr address: 15 h reset value: ffh for all these status bits the values can be mask = disable the interrupt general purpose port input register rd address: 16 h reset value: 00h 76543210 intem2 con pll frc sc2 sc c2 c4 c16/s con connection memory overflow indication mask pll pll source failure indication mask frc fr_comp failure indication mask sc2 sclk2 failure indication mask sc sclk failure indication mask c2 c2 failure indication mask c4 c4 failure indication mask c16/s c16 failure indication mask c16/s secondary reference failure indication mask (only in master mode) 0 = do not mask this interrupt 1= mask this interrupt 76543210 gppi gpb7 gpb6 gpb5 gpb4 gpb3 gpb2 gpb1 gpb0 gpb7..0 general purpose bits pef 20451 / 20471 / 24471 register description preliminary data sheet 84 2001-11-16 preliminary general purpose port output register wr address: 18 h reset value: 00h general purpose direction register rd/wr address: 1a h reset value: 00h general purpose mask register rd/wr address: 1b h reset value: ffh 76543210 gppo gpb7 gpb6 gpb5 gpb4 gpb3 gpb2 gpb1 gpb0 gpb7..0 general purpose bits 76543210 gpd dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 dc7..0 direction control 0 = set line as input 1 = set line as output 76543210 gpm im7 im6 im5 im4 im3 im2 im1 im0 im7..0 gpio interrupt mask (bit 0 for line 0, bit 1 for line 1 ..) 0 = enable change detection 1 = disable change detection pef 20451 / 20471 / 24471 register description preliminary data sheet 85 2001-11-16 preliminary general purpose interrupt register rd address: 1c h reset value: idcode time-slot value register rd address: 1e h reset value: xxh for the read time-slot value command the content of the tsv register is interpreted as: for the read configuration command the content of the tsv register is interpreted as: 76543210 gpi ind7 ind6 ind5 ind4 ind3 ind2 ind1 ind0 ind7..0 gpio interrupt indication (bit 0 for line 0, bit 1 for line 1 ..) 0 = no change detected 1 = at least one change detected on this line 76543210 tsv tsv7 tsv6 tsv5 tsv4 tsv3 tsv2 tsv1 tsv0 tsv7..0 time-slot value master/slave configuration only h-mode (page 68 ) tsv0 0 = slave 1 = master pll primary master configuration tsv3..0 see i3..0 from pll primary master reference selection command (page 68 ) tsv6..4 000 = 8 khz 001 = 512 khz 010 = 1.536 mhz pef 20451 / 20471 / 24471 register description preliminary data sheet 86 2001-11-16 preliminary 011 = 1.544 mhz 100 = 2.048 mhz 101 = 4.096 mhz 110 = 8.192 mhz 111 = 16.384 mhz pll secondary master configuration tsv3..0 see i3..0 from pll secondary master reference selection command (page 69 ) tsv6..4 000 = 8 khz 001 = 512 khz 010 = 1.536 mhz 011 = 1.544 mhz 100 = 2.048 mhz 101 = 4.096 mhz 110 = 8.192 mhz 111 = 16.384 mhz pll source selection tsv3..0 see i3..0 from pll source selection command (page 69 ) h.1x0 clock output selection only h-mode tsv1..0 see i1..0 from h.1x0 clock output selection command (page 70 ) pcm clock output selection tsv3..0 see i3..0 from pcm clock output selection command (page 70 ) compatibility clock output selection only h-mode tsv3..0 see i3..0 from compatibility clock output selection command (page 70 ) ct_netref_1 output selection only h-mode tsv3..0 see i3..0 from ct_netref_1 output selection command (page 71 ) tsv5..4 use tsv5..4, if tsv3..0 = 100x 00 = 8 khz 01 = 512 khz pef 20451 / 20471 / 24471 register description preliminary data sheet 87 2001-11-16 preliminary 10 = 2.048 mhz ct_netref_2 output selection only h-mode tsv3..0 see i3..0 from ct_netref_2 output selection command (page 71 ) tsv5..4 use tsv5..4, if tsv3..0 = 100x 00 = 8 khz 01 = 512 khz 10 = 2.048 mhz h.1x0 fallback mechanism and phase alignment tsv3..0 see i3..0 from h.1x0 fallback mechanism and phase alignment command (page 71 ) external frequency tsv0 see i0 from set external frequency command (page 74 ) parallel mode tsv0 see i0 from set parallel mode command (page 74 ) ireq pin tsv2..0 see i1..0 from set ireq pin command (page 75 ) h.1x0/pcm standby tsv1..0 see i0 from set h.1x0/pcm standby command (page 75 ) loop tsv1..0 see i1..0 from loop command (page 75 ) range of data rate tsv3..0 see i3..0 from set range of data rate command (page 76 ) pef 20451 / 20471 / 24471 register description preliminary data sheet 88 2001-11-16 preliminary for the read gpclk configuration command the content of the tsv register is interpreted as: for the read pcm and h.1x0 line configuration command the content of the tsv register is interpreted as: tsv0 0 = gpclk line as clock signal 1 = gpclk line as frame signal gpclk line as clock signal tsv3..1 000 = 8 khz 001 = 2.048 mhz 010 = 4.096 mhz 011 = 8.192 mhz 100 = 16.384 mhz 101 = input analog pll 110 = internal frequency gpclk line as frame signal tsv1 0 = rising edge 1 = falling edge tsv7..2 offset within the pfs frame in number of 16.384 mhz clock cycles (lower 6 bits; refer to con for the upper part) tsv1..0 00 = 2.048 mbit/s 01 = 4.096 mbit/s 10 = 8.192 mbit/s 11 = 16.384 mbit/s (only for pcm) pef 20451 / 20471 / 24471 register description preliminary data sheet 89 2001-11-16 preliminary in case of the read bit shift configuration command the content of the tsv register is interpreted as: configuration register rd address: 1f h reset value: xxh for the memory dump command (ccmd) the content of the con register is: for the read gpclk configuration command the content of the con register is: tsv0 edge control 0 = rising edge 1 = falling edge tsv3..1 bit shift value (range: 7 to 0) tsv4 byte shift value (only for input lines) 0 = bit shift applies to byte before pfs rising edge 1 = bit shift applies to byte before pfs falling edge 76543210 con con7 con6 con5 con4 con3 con2 con1 con0 con7..0 connection and data memory con7..5 width of the pulse in number of 16.384 mhz clock cycles from 1 to 8 i.e. con7..5 = 000 => 1 clock cycle, con7..5 = 010 => 3 clock cycles con4..0 offset within the pfs frame in number of 16.384 mhz clock cycles (upper 5 bits; refer to tsv for the lower part) pef 20451 / 20471 / 24471 register description preliminary data sheet 90 2001-11-16 preliminary 5.3 register overview for 16-bit interface table 21 register overview for 16-bit interface reg name access address reset value comment page no. sa rd/wr 00 h 0000 h source address register 91 da rd/wr 02 h 0000 h destination address register 91 gi rd/wr 04 h 0000 h general input register 92 cc16 rd/wr 06 h 0000 h connection command register 16-bit 92 cmd1 rd/wr 08h 00h configuration command register 1 this is a 8-bit register 68 cmd2 rd/wr 0ah 00h configuration command register 2 this is a 8-bit register 74 mv rd/wr 0ch 00h message value register this is a 8-bit register 78 ista1 rd 0eh 00h interrupt status register 1 this is a 8-bit register 78 iesta rd 10 h 0000 h interrupt error status register 93 intm1 rd/wr 12h 3dh interrupt mask register this is a 8-bit register 81 intem rd/wr 14 h ff3f h interrupt error mask register 93 idc rd 1c h idcode idcode register this is a 8-bit register 94 tsvc rd 1e h xxxx h time-slot value / configuration register 94 pef 20451 / 20471 / 24471 register description preliminary data sheet 91 2001-11-16 preliminary 5.4 detailed register description for 16-bit interface source address register rd/wr address: 00 h reset value: 0000 h destination address register rd/wr address: 02 h reset value: 0000 h 15 14 13 12 11 10 9 8 tsa7 tsa6 tsa5 tsa4 tsa3 tsa2 tsa1 tsa0 sa 76543210 bt 0 0 pa4 pa3 pa2 pa1 pa0 high see input time-slot address register on page 61 low see source port address register on page 61 15 14 13 12 11 10 9 8 tsa7 tsa6 tsa5 tsa4 tsa3 tsa2 tsa1 tsa0 da 76543210 bt 0 0 pa4 pa3 pa2 pa1 pa0 high see output time-slot address register on page 62 low see destination port address register on page 62 pef 20451 / 20471 / 24471 register description preliminary data sheet 92 2001-11-16 preliminary general input register rd/wr address: 04 h reset value: 0000 h connection command register 16-bit rd/wr address: 06 h reset value: 0000 h 15 14 13 12 11 10 9 8 gv15 gv14 gv13 gv12 gv11 gv10 gv9 gv8 gi 76543210 gv7gv6gv5gv4gv3gv2gv1gv0 gv15..0 general value gv15..8 see general input register 2 on page 65 gv7..0 see general input register 1 on page 63 15 14 13 12 11 10 9 8 0 0 osca2 osca1 osca0 isca2 isca1 isca0 cc16 76543210 i3 i2 i1 i0 cc3 cc2 cc1 cc0 high see subchannel address register on page 62 low see connection command register on page 66 pef 20451 / 20471 / 24471 register description preliminary data sheet 93 2001-11-16 preliminary interrupt error status register rd address: 10 h reset value: 0000 h interrupt error mask register rd/wr address: 14 h reset value: ff3f h 15 14 13 12 11 10 9 8 con pll frc sc2 sc c2 c4 c16/s iesta 76543210 0 0 nr2 nr1 ctb cta nw2 nw1 high see interrupt error status register 2 on page 80 low see interrupt error status register 1 on page 79 15 14 13 12 11 10 9 8 con pll frc sc2 sc c2 c4 c16/s intem 76543210 0 0 nr2 nr1 ctb cta nw2 nw1 high see interrupt error mask register 2 on page 83 low see interrupt error mask register 1 on page 82 pef 20451 / 20471 / 24471 register description preliminary data sheet 94 2001-11-16 preliminary idcode register rd address: 1c h reset value: idcode time-slot value / configuration register rd address: 1e h reset value: xxxx h 76543210 idc idc7 idc6 idc5 idc4 idc3 idc2 idc1 idc0 idc7..0 idcode refer to table 16 15 14 13 12 11 10 9 8 tsvc15 tsvc14 tsvc13 tsvc12 tsvc11 tsvc10 tsvc9 tsvc8 tsvc 76543210 tsvc7 tsvc6 tsvc5 tsvc4 tsvc3 tsvc2 tsvc1 tsvc0 tsvc15..8 configuration and connection data memory (refer to page 89 ) tsvc7..0 time-slot value (refer to page 85 ) pef 20451 / 20471 / 24471 programming the device preliminary data sheet 95 2001-11-16 preliminary 6 programming the device the register set consists of parameter registers ( spa , itsa , sca , dpa , otsa , gi1 ..), command registers ( ccmd , cmd1 , cmd2 ) and status registers ( ista1 , iesta1 , iesta2 ). please note that some bits contained in the register ista1 (interrupt status register 1) do not generate any interrupt, for more details see the paragraph chapter 6.2 . before issuing a command the parameter registers have to be written accordingly. a connection command can only be issued if the connection command register is ready to be written to (see figure 25 ). the connection command register status is shown with the rdy bit in the ista1 register. a detailed description for the read and write access to the command registers can be found in chapter 6.1 . figure 25 order of register access command register ready? write parameter registers write command register n y command register ready? write parameter registers write command register n y passive w aiting with interrupt active waiting (polling) without interrupt switi_032.emf pef 20451 / 20471 / 24471 programming the device preliminary data sheet 96 2001-11-16 preliminary 6.1 read and write access for the read and write access it is necessary to distinguish between a connection and configuration command. the connection command register is used to establish a connection (described in chapter 6.11 ) and the configuration registers are used to configure the device, i.e. set the clock frequency. if the ista1 :rdy bit is set the connection command register is ready to receive data from the p interface. if the parameter register and the connection command register are written the rdy bit will be reset from the internal controller. if the connection is established the internal controller will set the rdy bit and the connection command register is ready for the next write or read access. the ista1 :rdy can be enabled to generate an interrupt to indicate that the device is ready to receive the data, otherwise the p must poll the ista1 :rdy bit. the configuration command register works independent from the rdy bit. note: there must be a recovery time period of 120 ns after every configuration command write access to the next write access (command or parameter register). pef 20451 / 20471 / 24471 programming the device preliminary data sheet 97 2001-11-16 preliminary 6.2 interrupt handling the switi interrupt concept consists of four interrupt status register with their corresponding mask register. the five interrupt status register can be divided in one main register, and two error interrupt register, one general purpose interrupt register and one time-slot value register. every secondary status register and the time-slot value register has a bit in the main register to indicate the set of an interrupt in the assigned error or general purpose register or to indicate a new value in the time-slot value register. the interrupt status register can be read via the microprocessor interface. the nfc and rdy will be set and reset from the internal controller. when an interrupt occurs one or more of the bit gpio, tsa, er2, or er1 is set, then the assigned secondary interrupt status register or time-slot value register must be read first in order to check for the cause of the interrupt. after a secondary status register read access, the error status register and the corresponding bit in the interrupt status register 1 (ista1) will be reset. figure 26 8-bit p access interrupt structure the ireq output is level active. it stays active until all interrupt sources have been serviced. if a new status bit is set while an interrupt is being serviced (p read access), the ireq pin stays active. for the duration of a write access to the intm1 register the ireq line is deactivated. when using an edge-triggered interrupt controller, it is thus recommended to rewrite the intm1 register at the end of any interrupt service routine. apll, str, rdy and nfc bits if the internal controller does set the rdy bit for the first time and the bit is not masked an interrupt will be generated. if the p reads the ista1 register the interrupt will be deactivated. the rdy bit is still active and can be reset from the internal controller. the nfc, str and apll bits are not set by any interrupt and therefore can not be masked. setting these bit does not generate any interrupt. the nfc bit is set from the internal controller if no further connections can be established. the str bit is set from the internal stream to stream controller if a stream to stream connection is configured. the apll bit is set from the internal analog pll controller if the pll is locked. interrupt error status register 2 interrupt error status register 1 time slot value register general purpose interrupt status register switi_063.emf apll str er2 er1 gpio tsa nfc rdy main status register pef 20451 / 20471 / 24471 programming the device preliminary data sheet 98 2001-11-16 preliminary masking interrupts if an interrupt is not masked (enabled) the ireq pin will be active if one of the status bits in the interrupt status register is set. the mask bit prevents that the ireq pin will be active if the status bit is set. the mask bits for the error status registers or general purpose interrupt register disables the interrupt indication for the interrupt status register. only the interrupt status register can set the ireq pin if the bit is not masked. interrupt structure for a 16-bit microprocessor access figure 27 16-bit p access interrupt structure in opposite to the 8-bit p access there is only one bit (er1) to indicate a change in the 16-bit interrupt error status register 1. er1 gpio tsa nfc rdy interrupt error status register 1 time slot value register str switi_068.emf apll pef 20451 / 20471 / 24471 programming the device preliminary data sheet 99 2001-11-16 preliminary 6.3 command and register overview the following table ( table 22 ) shows which parameter registers are considered by issuing an appropriate connection command. table 22 affected registers for connection commands command registers spa itsa sca dpa otsa mv gi1 gi2 con connect/disconnect (without subchannels) xx x x connect (with subchannels) xx xx x disconnect (with subchannels) xx x x send message x x x stop message x x disconnect part of broadcast (without subchannels) xx x x disconnect part of broadcast (with subchannels) xx xx x multipoint connect/ disconnect xx x x bidirectional connection x x x x disconnect all memory dump (connection and data memory) x pef 20451 / 20471 / 24471 programming the device preliminary data sheet 100 2001-11-16 preliminary the following table ( table 23 ) shows which parameter registers are considered by issuing an appropriate configuration command. table 23 affected registers for configuration commands command registers cmd1 cmd2 spa itsa sca dpa otsa gi1 gi2 tsv set h.1x0 master/ slave x pll primary master ref. xx pll secondary master ref. xx pll source selection x h.100/h.110 clock output x pcm clock output x comp. clock output x ct_netref_1(2 ) output x h.100/h.110 fallback x set bit rate local bus xx x set bit rate h.100/h.110 xx read time-slot x x x x x stream to stream switch xx x clock shift x x x external input frequency x set parallel mode x set ireq pin x pef 20451 / 20471 / 24471 programming the device preliminary data sheet 101 2001-11-16 preliminary the command registers have the following structure: cc3..0 is the command code and i3..0 is the parameter code. the following tables ( table 24 to table 25 ) show all valid values of command and parameter codes and the related function. pcm and h.1x0 standby x set loop x frame signal x x x gpclk clock x x set range of data rate x read configuration xx read gpclk configuration xx read pcm line configuration xx read h.1x0 line configuration xx read bit shift configuration xx software reset x 76543210 i3 i2 i1 i0 cc3 cc2 cc1 cc0 table 23 affected registers for configuration commands (cont ? d) command registers cmd1 cmd2 spa itsa sca dpa otsa gi1 gi2 tsv pef 20451 / 20471 / 24471 programming the device preliminary data sheet 102 2001-11-16 preliminary table 24 connection command and parameter codes command 1) 1) the input port is determined in spa bit4..0 and the output port in dpa bit4..0. the input time-slot is determined in itsa and the output time-slot in otsa. command code (low nibble) parameter code (high nibble) note constant delay connect disconnect 1 h 5 h 0 h 1 h 2 h 3 h address 8-bit connections address 4-bit connections address 2-bit connections address 1-bit connections minimum delay connect 2 h x h send message 3 h x h stop message 4 h x h disconnect part of broadcast 6 h 0 h 1 h 2 h 3 h address 8-bit connections address 4-bit connections address 2-bit connections address 1-bit connections multipoint connect 7 h 0 h 1 h or connection of time-slots and connection of time-slots disconnect all 8 h x h bidirectional connect 9 h 0 h 1 h minimum delay constant delay memory dump a h 0 h 1 h disable enable pef 20451 / 20471 / 24471 programming the device preliminary data sheet 103 2001-11-16 preliminary table 25 configuration command 1 and parameter codes command command code (low nibble) parameter code (high nibble) note set bit rate local bus 1) 1) the input and output port is determined in spa , dpa b h 0-3 h 4-7 h 8-b h c-f h no effect set bit rate of local input port (2/4/8/ 16 mbit/s) set bit rate of local output port (2/4/8/16 mbit/s) set for both input and output (2/4/8/16 mbit/s) set bit rate h.100/h.110 bus 2) 2) the port is determined in spa c h 0 h 1 h 2 h 3 h set bit rate of port# to 2 mbit/s set bit rate of port# to 4 mbit/s set bit rate of port# to 8 mbit/s set bit rate for all ports to 8 mbit/s read time-slot 3) 3) the time-slot is determined in spa and itsa or dpa and otsa d h 0 h 1 h read time-slot of input port read time-slot of output port stream-to- stream 4) 4) source and destination are determined in spa , dpa e h 0 h 4 h 1 h 5 h 2 h 6 h 3 h 7 h 8 h -ff h release connection w. mode 0 5) establish connection w. mode 0 release connection w. mode 1 establish connection w. mode 1 release connection w. mode 2 establish connection w. mode 2 release connection w. mode 3 establish connection w. mode 3 release all programmed stream to stream connections 5) see ? stream-to-stream connection mapping ? on page 28 bit shift 6) 6) the input line is determined in spa , the shift information in gi1 f h 0 h 1 h 2 h 3 h set bit shift of input line set bit shift of all input lines set bit shift of all output lines set bit shift of all input and output lines pef 20451 / 20471 / 24471 programming the device preliminary data sheet 104 2001-11-16 preliminary table 26 configuration command 2 and parameter code command command code (low nibble) parameter code (high nibble) note external frequency 1 h 0 h 1 h set frequency to 32.768 mhz set frequency to 16.384 mhz parallel mode 2 h 0 h 1 h disable enable = first 8 local input bus lines are parallel and first 8 local output lines are parallel set ireq pin 3 h 0 h 1 h 2 h 4 h 5 h 6 h ireq is active low, timer = 20 ns ireq is active high, timer = 20 ns ireq as open-drain, timer = 20 ns ireq is active low, timer = 300 ns ireq is active high, timer = 300 ns ireq as open-drain, timer = 300 ns pcm - h.1x0 standby 4 h 0 h 1 h 2 h 3 h disable pcm and h-bus enable pcm and disable h-bus disable pcm and enable h-bus enable pcm and h-bus loop 5 h 0 h 1 h 2 h 3 h no loop at all enable pcm and disable h-bus loop disable pcm and enable h-bus loop enable pcm and h-bus loop frame signal 1) 6 h 0xxx b 1xxx b signal is high active signal is low active xxx is the line address gpclk as clock 2) 7 h 0 h -7 h parameter code is line address range of data rate 8 h 0 h -6 h 8 h -a h logical or connection from min. and max. codes pef 20451 / 20471 / 24471 programming the device preliminary data sheet 105 2001-11-16 preliminary read configuration 3) 9 h 0 h 1 h 2 h 3 h 4 h 5 h 6 h 7 h 8 h 9 h a h b h c h d h e h f h master/slave configuration pll primary reference - master pll secondary ref. - master pll source - slave clock output selection - h.1x0 clock output selection - pcm clock ouput selection for interoperability signals output selection - ct_netref_1 output selection - ct_netref_2 h.1x0 fallback - phase alignment external input frequency parallel mode ireq pin h.1x0/pcm standby loop range of data rate read gpclk configuration 4) a h 0 h -7 h parameter code is line address read pcm line configuration 5) b h 0 h 1 h data rate of input line 6) data rate of output line 7) read h.1x0 line configuration 8) c h - data rate of h.1x0 line 9) read bit shift configuration 10) d h 0 h 1 h shift value for input line 9) shift value for all output lines 1) offset and width are determined in gi1 and gi2 2) frequency is determined in gi1 3) the result can be read from the tsv register 4) the result can be read from the tsv and con register 5) the result can be read from the tsv register 6) spa must be used for line number 7) dpa must be used for line number 8) the result can be read from the tsv register 9) spa must be used for line number 10) the result can be read from the tsv register table 26 configuration command 2 and parameter code (cont ? d) command command code (low nibble) parameter code (high nibble) note pef 20451 / 20471 / 24471 programming the device preliminary data sheet 106 2001-11-16 preliminary 6.4 indirect configuration register access it is possible to read the current switi configuration with an indirect register access for analyze and test purpose. there are five commands in the cmd2 register which can be used to read the configuration. the clock generator output signal and external configuration for the switi can be read with the ? read configuration command ? . the four instruction bits select one possible configuration command. the current configuration is determined by the command written in the tsv register. the configuration information for every command can be found on page 58 . the line configuration can be read with two commands ? read pcm line configuration ? and ? read h.1x0 line configuration ? . before one of these commands will be issued the spa or dpa register must be written with the port number. the configuration for the selected line is written in the tsv register by the internal controller. the interrupt handling is described in chapter 6.2 . the bit shift configuration can be read with the command ? read bit shift configuration ? and the dataflow is the same as described above. with the command ? read gpclk configuration ? it is possible to read the configuration for every gpclk line. if this command was written the configuration can be read from the tsv and con register. the con register is not interrupt controlled and will keep the last data after a microprocessor read access. to read the correct configuration data from the tsv register it is not allowed to use the command "read time-slot value" before the tsv register was read. pef 20451 / 20471 / 24471 programming the device preliminary data sheet 107 2001-11-16 preliminary 6.5 initialization procedure after the reset process the pll, h.1x0 interface, pcm interface, and some other signals need to be initialized. since the switi offers the possibility to use two different external crystal/oscillator frequencies the command ? set external frequency ? must be used first to set the correct frequency and to set the correct value of the input frequency for the apll. after approximately 750 s the apll is locked and the apll status bit is set and the next commands can be written. figure 28 initialization procedure after reset reset (hardware) internal frequency = ext. frequency write 41 h to c m d 2 (if ext. freq. = 32.768 m h z) write 51 h to c m d 2 (if ext. freq. = 16.384 m h z) wait ~750s read interrupt status register 1 ista1:apll = 1 ? apll is locked int. frequency = 49.152 mhz y n switi_073.emf pef 20451 / 20471 / 24471 programming the device preliminary data sheet 108 2001-11-16 preliminary after this initialization procedure the different functional blocks of the switi can be programmed. ? h.1x0 interface ? pcm interface ? interrupt ? s and ireq pin ? gpclk ? s and frame signals ? general purpose interface 6.6 h.1x0 clocking unit if the htsi in h-mode is used the the clock generator (pll) for the h.1x0 interface must be programmed first. this chapter can be skipped for the m-mode. for the pll synchronization please refer to chapter 3.4.5 on page 36 . they are three program sequences for the h.1x0 interface: ? program the h.1x0 fallback mechanism and pll inputs for h.1x0 master or slave ? program all output clock signals for the master configuration ? program the frame signals for the slave configuration program the pll source and h.1x0 clock fallback the program sequence for the pll source programming and/or h.1x0 clock fallback must be finished with the command ? h.1x0 master/slave selection ? in the cmd1 register. whenever the pll source or the h.1x0 clock fallback was changed the h.1x0 master/ slave selection ? command must be programmed after this changes example: a typical h.100 master or slave configuration is shown in figure 29 . slave configuration: ? ct_c8_a as pll input reference ? enable clock monitoring (ct_c8_a, ct_c8_b) ? enable automatic clock fallback from ct_c8_a to ct_c8_b h.100 primary master configuration: ? ntwk_1 = 8 khz as primary pll reference ? ct_netref = 1.544 mhz as fallback pll reference ? enable automatic clock fallback for the primary master ? enable automatic switch back to ntwk_1 if ntwk_1 returns h.100 secondary master configuration ? ct_c8_a as primary pll reference ? ntwk_1 = 8 khz as fallback pll reference ? enable automatic clock fallback for the secondary master to ntwk_1 pef 20451 / 20471 / 24471 programming the device preliminary data sheet 109 2001-11-16 preliminary figure 29 h.100 master and slave configuration process program the output clocks example: htsi in h-mode is configured as h.100 primary master and ct_c8_a with / ct_frame_a shall be driven and the mvip-90 clock signals shall be driven. if h.100 primary master is configured then ? write 15 h to cmd1 ? write 17 h to cmd1 example: htsi in h-mode is configured as h.100 secondary master and the ct_b clocks shall be driven. if h.100 secondary master is configured then ? write 25 h to cmd1 switi_074.emf pll is locked select ct_a as pll source write 54 h to cmd1 enable automatic clock fallback with clock monitoring write ba h to cmd1 set the h.1x0 interface as slave write 01 h to cmd1 h.1x0 slave is configured h.1x0 as slave select ntwk_1 (8 khz) as primary pll source write 00 h to gi1 write 52 h to cmd1 h.100 as primary master h.100 as secondary master select ct_a clocks as pll primary source write 72 h to cmd1 select ct_netref (1.544 mhz) as secondary pll source write 03 h to gi1 write 13 h to cmd1 enable automatic fallback mechanism. enable automatic switch back to prim. source write 5a h to cmd1 set the h.100 interface as master write 11 h to cmd1 h.100 primary master is configured select ntwk_1 (8 khz) as pll secondary source write 00 h to gi1 write 33 h to cmd1 enable automatic fallback mechanism. for secondary master write 2a h to cmd1 set the h.100 interface as master write 11 h to cmd1 h.100 secondary master is configured pef 20451 / 20471 / 24471 programming the device preliminary data sheet 110 2001-11-16 preliminary example: htsi in h-mode is configured as h.100 slave and the ct_netref_1 signal shall be provided. the signal is inverted and the source signal is ntwk_1. if h.100 slave is configured then ? write 38 h to cmd1 6.7 pcm clocking unit if the htsi in h-mode is used the h.1x0 clock generator must be programmed first. the pcm clock signals for the line interface will be provided from external pcm devices if the switi is used as pcm clock slave or will be provided from the internal pll if the switi is used as pcm clock master. this pcm clock configuration can be programmed with the special command ? pcm input/output selection ? in the figure cmd1 register. for the pll synchronization please refer to chapter 3.4.5 on page 36 . example: htsi in m-mode as pcm clock master, pll reference is ntwk_1 with 8 khz and pdc is driven with 8.192 mhz and pfs is driven. ? write 00 h to gi1 ? write 52 h to cmd1 ? write b6 h to cmd1 example htsi in m-mode as pcm clock slave, pll reference is pdc with 4.096 mhz. ? write 05 h to gi1 ? write 22 h to cmd1 ? write 26 h to cmd1 (pdc = 4.096 mhz and pfs as input) 6.8 h.1x0/pcm line interface 6.8.1 standby command all h.1x0 and pcm lines are in a high impedance state after the reset process. if they are configured (data rate, bit shift) they can be enabled with the standby command. during the normal operation the pcm and h.1x0 lines can be enabled or disabled with the standby command. if the lines are disabled the device works internally like an active device. pef 20451 / 20471 / 24471 programming the device preliminary data sheet 111 2001-11-16 preliminary example: set all output pcm lines to high impedance. ? write 24 h to cmd1 (i1 must be set to ? 1 ? because only pcm shall be tristated) 6.8.2 determining clock rates the data rate range command is necessary to optimize the minimum delay feature. after the reset process the device assumes a bit rate of 2.048 mbit/s for all pcm and h.1x0 lines. the command must be issued if other data rates are used. example (8-bit p interface): 1. specify that only 2.048 mbit/s and 4.096 mbit/s are used for following set bit rate command. ? write 38 h to cmd2 2. set bit rate of 4.096 mbit/s on local bus input line 8 and local bus output line 1 ? write 08 h to spa ? write 01 h to dpa ? write db h to cmd1 3. set bit rate of 2.048 mbit/s on h-bus line 8 ? write 88 h to spa ? write 0c h to cmd1 example (16-bit p interface): 1. ? write 38 h to cmd2 2. ? write 0008 h to sa ? write 0001 h to da ? write db h to cmd1 3. ? write 0008 h to sa ? write 0c h to cmd1 pef 20451 / 20471 / 24471 programming the device preliminary data sheet 112 2001-11-16 preliminary 6.8.3 performing bit shifting the bit shift is performed on half-bit steps, not on a clock basis. it is a true bit shift, it means that with a data rate equals to the data clock frequency (e.g. 4.096 mbit/s with 4.096 mhz data clock) programming a bit shift of 1-bit results on a shift of 1 clock period, and programming a shift of half-bit the result is a shift of half clock period. running in double data clock rate (e.g. 4.096 mbit/s with 8.192 mhz data clock), a bit shift of 1-bit results on a shift of 2 clock periods and a shift of half-bit will result on a shift of 1 clock period. 6.8.3.1 input bit shifting figure 30 example: input bit shifting example (8-bit p interface): begin time-slot 0 of local input line 8 with the 4th rising edge relative to one byte before the pfs rising edge. the bits are internally sampled with the falling edge. ? write 08 h to spa ? write 08 h to gi1 ? write 0f h to cmd1 example (16-bit p interface): ? write 0008 h to sa ? write 0008 h to gi ? write 0f h to cmd1 pfs 0 1 7 local bus input line 8 23 ts 0 4 switi_040.emf 0 data rate of the selected line pef 20451 / 20471 / 24471 programming the device preliminary data sheet 113 2001-11-16 preliminary 6.8.3.2 output bit shifting figure 31 example: output bit shifting example (8-bit p interface): output time-slot 0 of all output lines begins with the first falling edge relative to the first byte after pfs rising edge. the bits are internally sampled with the rising edge. ? write 01 h to gi1 ? write 2f h to cmd1 example (16-bit p interface): ? write 0001 h to gi ? write 2f h to cmd1 pfs 0 1 7 local bus output lines 2 ts 0 switi_041.emf data rate of the line pef 20451 / 20471 / 24471 programming the device preliminary data sheet 114 2001-11-16 preliminary 6.9 global clock signals 6.9.1 framing groups figure 32 example framing groups example (8-bit p interface): frame signal on gpclk_1 starts with the rising edge of 64th clock cycle and the length is set to 244 ns (4 x 61 ns). ? write 00 h to gi1 ? write 61 h to gi2 ? write 16 h to cmd2 125s 01 125s 64 01 4 4 pfs 16.384 mbit/s gpclk_1 gpclk_2 switi_077.emf 427ns 244ns 125s pef 20451 / 20471 / 24471 programming the device preliminary data sheet 115 2001-11-16 preliminary frame signal on gpclk_2 starts with the falling edge of the 4th clock cycle and the length is set to 427 ns (7 x 61 ns). ? write 12 h to gi1 ? write c0 h to gi2 ? write 26 h to cmd2 example (16-bit p interface): ? write 6100 h to gi2 ? write 0016 h to cmd2 ? write c012 h to gi2 ? write 0026 h to cmd2 6.10 read time-slot value by issuing this command the time-slot value appears in the register tsv after arriving and an interrupt will be caused and a new read time-slot value will be accepted. the command has to be issued for every read request. the current tsv data will be overwritten if the read time-slot command is issued. example (8-bit p interface): read time-slot 10 of local bus input line 3 ? write 03 h to spa ? write 0a h to itsa ? write 0d h to cmd1 example (16-bit p interface): ? write 0a03 h to sa ? write 0d h to cmd1 wrong time-slot and time-out in some case it could be happen that the p tries to read a wrong time-slot. a wrong time- slot is defined as a invalid time-slot number for the selected data rate, i.e. data rate = 2 mbit/s and selected time-slot is 58. if the p tries to read a wrong time-slot no interrupt would be generated and the controller doesn ? t accept any further commands. the switi has a integrated time-out counter to allow a new read time-slot command after the maximum of three frames. pef 20451 / 20471 / 24471 programming the device preliminary data sheet 116 2001-11-16 preliminary 6.11 establish connections the following chapter describes the programming of several kinds of connections. the programming interface allows to program or re-program a connection during the normal switching mode. before a new connection for a specific output time-slot and line will be programmed the specific connection has to be released. 6.11.1 establish 8-bit connections figure 33 example: 8-bit connection example (8-bit p interface): connect time-slot 10 of local bus line 3 with output time-slot 30 of h-bus line 22 as a constant delay connection ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 96 h to dpa ? write 01 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 1e96 h to da ? write 0001 h to cc16 local bus input line 3 h-bus i/o line 22 constant delay frame signal ts 30 ts 10 switi_027.emf pef 20451 / 20471 / 24471 programming the device preliminary data sheet 117 2001-11-16 preliminary 6.11.2 subchannel switching with the subchannel address register ( sca ) and the constant delay command it is possible to program 1,2, and 4 connections. the following figure explains the relation between the subchannel address and the corresponding bits in one time-slot. figure 34 subchannel address in time-slot 6.11.2.1 establish 4-bit connections figure 35 example: 4-bit connection 1 0 isca from sca register osca from sca register 1 2 3 0 3 1 2 4 0 5 6 7 1 3 2 0 1 0 2 3 ts in 6 1 3 4 0 5 2 7 1 0 2 3 1 0 ts out 0 h 1 h 1 h 6 h 1 h 3 h 2 h 3 h switi_070.emf local bus input line 3 h-bus i/o line 22 constant delay frame signal ts 30 ts 10 switi_028.emf pef 20451 / 20471 / 24471 programming the device preliminary data sheet 118 2001-11-16 preliminary example (8-bit p interface): connect low nibble of time-slot 10 of local bus line 3 with high nibble of output time-slot 30 of h-bus line 22 as a constant delay connection ? write 08 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 96 h to dpa ? write 11 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 1e96 h to da ? write 0811 h to cc16 6.11.2.2 establish 2-bit connections figure 36 example: 2-bit connection example (8-bit p interface): connect 2nd 2-bit subchannel of time-slot 10 of local bus line 3 with 4th 2-bit subchannel of output time-slot 30 of h-bus line 22 as a constant delay connection ? write 19 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 96 h to dpa ? write 21 h to ccmd local bus input line 3 h-bus i/o line 22 constant delay frame signal ts 30 ts 10 switi_042.emf pef 20451 / 20471 / 24471 programming the device preliminary data sheet 119 2001-11-16 preliminary example (16-bit p interface): ? write 0a03 h to sa ? write 1e96 h to da ? write 1921 h to cc16 6.11.2.3 establish 1-bit connections figure 37 example: 1-bit connection example (8-bit p interface): connect 3rd 1-bit subchannel of time-slot 10 of local bus line 3 with 6th 1-bit subchannel of output time-slot 30 of h-bus line 22 as a constant delay connection ? write 2a h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 96 h to dpa ? write 31 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 1e96 h to da ? write 2a31 h to cc16 local bus input line 3 h-bus i/o line 22 constant delay frame signal ts 30 ts 10 switi_043.emf pef 20451 / 20471 / 24471 programming the device preliminary data sheet 120 2001-11-16 preliminary 6.11.3 establish broadcast connections figure 38 example: broadcast connection example (8-bit p interface): connect time-slot 10 of local bus line 3 with output time-slot 30 of h-bus line 22 and output time-slot 98 of h-bus line 29 in constant delay mode. if the connections are established consecutively it is not necessary to rewrite the source determining registers itsa and spa because they keep their values. ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 96 h to dpa ? write 01 h to ccmd ? write 62 h to otsa ? write 9d h to dpa ? write 01 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 1e96 h to da ? write 0001 h to cc16 ? write 629d h to da ? write 0001 h to cc16 local bus input line 3 h-bus i/o line 22 constant delay frame signal ts 30 ts 10 h-bus i/o line 29 ts 98 switi_031.emf pef 20451 / 20471 / 24471 programming the device preliminary data sheet 121 2001-11-16 preliminary 6.11.4 establish subchannel broadcast connection figure 39 example: subchannel broadcast connection ? first connection ? write 03 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 00 h to dpa ? write 21 h to ccmd ? second connection ? write 1a h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 00 h to dpa ? write 21 h to ccmd ? third connection ? write 23 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 00 h to dpa ? write 31 h to ccmd ? fourth connection ? write 2a h to sca ? write 0a h to itsa ? write 03 h to spa local bus input line 3 local bus output line 0 constant delay frame signal ts 30 ts 10 switi_084.emf 1 2 3 4 5 pef 20451 / 20471 / 24471 programming the device preliminary data sheet 122 2001-11-16 preliminary ? write 1e h to otsa ? write 00 h to dpa ? write 31 h to ccmd ? fifth connection ? write 08 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 00 h to dpa ? write 21 h to ccmd 6.11.5 establish multipoint connection figure 40 example: multipoint connection example (8-bit p interface): connect time-slot 10 of local bus line 3 and time-slot 20 of local bus line 8 logical or with output time-slot 30 of h-bus line 22 in constant delay mode. if the connections are established consecutively it is not necessary to rewrite the destination determining registers otsa and dpa because they keep their values. ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 96 h to dpa ? write 07 h to ccmd ? write 14 h to itsa ? write 08 h to spa ? write 07 h to ccmd local bus input line 3 h-bus i/o line 22 constant delay frame signal ts 30 ts 10 local bus input line 8 ts 20 or sw iti_034.em f pef 20451 / 20471 / 24471 programming the device preliminary data sheet 123 2001-11-16 preliminary example (16-bit p interface): ? write 0a03 h to sa ? write 1e96 h to da ? write 0007 h to cc16 ? write 1408 h to sa ? write 0007 h to cc16 6.12 send messages sending messages means to transmit a constant value on any time-slot or subchannel after the message is programmed within three frames. that means a message has always a minimum delay and is sent until the sending is stopped by the stop message command. figure 41 example: send message example (8-bit p interface): send constant value of ff h on time-slot 10 of local bus line 3 ? write ff h to mv ? write 0a h to otsa ? write 03 h to dpa ? write 03 h to ccmd example (16-bit p interface): ? write ff h to mv ? write 0a03 h to da ? write 0003 h to cc16 local bus output line 3 ts 10 ff h frame signal switi_029.emf pef 20451 / 20471 / 24471 programming the device preliminary data sheet 124 2001-11-16 preliminary 6.13 release connections 6.13.1 release 8-bit connections example (8-bit p interface): release connection established in figure 33 ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 96 h to dpa ? write 05 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 1e96 h to da ? write 0005 h to cc16 6.13.2 release 4-bit connections example (8-bit p interface): release connection established in figure 35 ? write 08 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 96 h to dpa ? write 15 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 1e96 h to da ? write 0815 h to cc16 6.13.3 release 2-bit connections example (8-bit p interface): release connection established in figure 36 ? write 19 h to sca ? write 0a h to itsa ? write 03 h to spa pef 20451 / 20471 / 24471 programming the device preliminary data sheet 125 2001-11-16 preliminary ? write 1e h to otsa ? write 96 h to dpa ? write 25 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 1e96 h to da ? write 1925 h to cc16 6.13.4 release 1-bit connections example (8-bit p interface): release connection established in figure 37 ? write 2a h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 96 h to dpa ? write 35 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 1e96 h to da ? write 2a35 h to cc16 pef 20451 / 20471 / 24471 programming the device preliminary data sheet 126 2001-11-16 preliminary 6.13.5 release broadcast connection example (8-bit p interface): release connection established in figure 38 . all but the last connection participating on a broadcast connection have to be released by the disconnect part of broadcast command. the last connection has to be released by the constant delay connect disconnect command. ? write 0a h to itsa ? write 03 h to spa ? write 62 h to otsa ? write 9d h to dpa ? write 06 h to ccmd ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 96 h to dpa ? write 05 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 629d h to da ? write 0006 h to cc16 ? write 0a03 h to sa ? write 1e96 h to da ? write 0005 h to cc16 6.13.6 release subchannel broadcast connection the order can be different as the establish order. the last release must be a normal release command. ? first connection ? write 03 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 00 h to dpa ? write 26 h to ccmd ? second connection ? write 1a h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa pef 20451 / 20471 / 24471 programming the device preliminary data sheet 127 2001-11-16 preliminary ? write 00 h to dpa ? write 26 h to ccmd ? third connection ? write 23 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 00 h to dpa ? write 36 h to ccmd ? fourth connection ? write 2a h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 00 h to dpa ? write 36 h to ccmd ? fifth connection ? write 08 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 00 h to dpa ? write 25 h to ccmd 6.13.7 release multipoint connection this type of connections is released with normal disconnect commands. (see ? release 8-bit connections ? on page 124. ) 6.14 stop sending messages example (8-bit p interface): stop sending message invoked in figure 41 ? write 0a h to otsa ? write 03 h to dpa ? write 04 h to ccmd example (16-bit p interface): ? write 0a03 h to da ? write 0004 h to cc16 pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 128 2001-11-16 preliminary 7 timing diagrams 7.1 pcm interface timing the following tables and figures give the pcm timing with a capacitive load of 50 pf. pdc and pfs are configured as inputs. the timing is also valid if pdc and pfs are configured as outputs.the pfs output high time is fixed to 488 ns for all data rates and clock rates.the pfs input minimum high time depends on the pdc input frequency (see table table 27 ) figure 42 pcm timing t d o u t t sin t h i n t clk_h t f s pfs pdc in out t clk_l t hfs t f t r bit 7 bit 6 bit 7 bit 6 t p f s switi_057.emf t sfs ts0 ts63 4mbit/s pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 129 2001-11-16 preliminary table 27 pcm timing parameter symbol limit values unit test condition min. max. period pfs t pfs 125 s pfs high time t fs 480 ns pdc = 2.048 mhz pfs set up time to clock t sfs 15 ns pfs hold time from clock t hfs 20 ns pfs high time t fs 240 ns pdc = 4.096 mhz pfs set up time to clock t sfs 15 ns pfs hold time from clock t hfs 20 ns pfs high time t fs 120 ns pdc = 8.192 mhz pfs set up time to clock t sfs 10 ns pfs hold time from clock t hfs 20 ns pfs high time t fs 60 ns pdc = 16.384 mhz pfs set up time to clock t sfs 10 ns pfs hold time from clock t hfs 20 ns pdc clock period t clk 480 ns pdc = 2.048 mhz pdc clock period low t clk_l 232 251 ns pdc clock period high t clk_h 233 252 ns pdc clock period t clk 240 ns pdc = 4.096 mhz pdc clock period low t clk_l 112 131 ns pdc clock period high t clk_h 113 132 ns pdc clock period t clk 120 ns pdc = 8.192 mhz pdc clock period low t clk_l 51 70 ns pdc clock period high t clk_h 52 71 ns pdc clock period t clk 60 ns pdc = 16.384 mhz pdc clock period low t clk_l 26 34 ns pdc clock period high t clk_h 27 35 ns pdc rise time t r 10 ns pdc fall time t f 10 ns pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 130 2001-11-16 preliminary serial data input set up time t sin 20 ns pdc = 2.048 mhz serial data input hold time t hin 30 ns serial data input set up time t sin 20 ns pdc = 4.096 mhz serial data input hold time t hin 30 ns serial data input set up time t sin 20 ns pdc = 8.192 mhz serial data input hold time t hin 30 ns serial data input set up time t sin 20 ns pdc = 16.384 mhz serial data input hold time t hin 30 ns serial data output delay t dout 030 1) ns pdc = 2.048 mhz serial data output delay t dout 030 1) ns pdc = 4.096 mhz serial data output delay t dout 030 1) ns pdc = 8.192 mhz serial data output delay t dout 030 1) ns pdc = 16.384 mhz 1) for pcm master, the maximum delay is 15 ns table 27 pcm timing (cont ? d) parameter symbol limit values unit test condition min. max. pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 131 2001-11-16 preliminary 7.2 pcm parallel mode timing figure 43 parallel mode timing table 28 pcm parallel mode timing parameter symbol limit values unit test condition min. max. frame setup time to clock t fs 125 ns frame hold time to clock t fh 125 ns input data setup time t ds 50 ns input data hold time t dh 15 ns output data delay t dd 35 ns pdc clock period t clk 483 493 ns pdc = 2.048 mhz pdc clock period high t clk_h 231 257 ns pdc clock period low t clk_l 231 257 ns switi_071.emf time slot pdc pfs in out 2550123 t fs t fh t clk t clk_h t dh t ds t dd ts1 valid data ts3 valid data t clk_l pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 132 2001-11-16 preliminary 7.3 h-bus and pcm (local bus) frame structure figure 44 shows the h-bus clock alignment together with the pcm (local bus) clock alignment. figure 44 h-bus and pcm (local bus) clock alignment ct_frame(a/b) ct_c8(a/b) fr_comp c16 c2 c4 sclk (2.048mhz) sclk (4.096mhz) sclk (8.192mhz) sclkx2* (2.048mhz) sclkx2* (4.096mhz) sclkx2* sclk-d (8.192mhz) sw iti_079.em f pdc@8 mhz pdc@4 mhz pdc@2 mhz pfs pdc@16 mhz frame boundary pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 133 2001-11-16 preliminary figure 45 h-bus frame structure figure 46 h.1x0 detailed functional timing figure 47 h.1x0 functional timing for 8, 4 and 2 mbit/s data streams 1 3 4 5 6 7 8 2 8 2 3 4 5 6 7 8 1 1 0 127 125 s switi_006.emf ct_frame ct_c8 ct_dx time slot 1 bit cell bit 8 bit 1 switi_012.emf ct_frame ct_c8 data o ut data in 3 4 5 6 7 8 2 8 2 3 4 5 6 7 1 1 8 125 s switi_064.e ct_frame ct_dx 8 mbit/s ct_dx 2 mbit/s ct_c8 1 2 3 4 5 6 7 2 7 1 8 8 1 ct_dx 4 mbit/s 1 1 8 8 time-slot 0 time-slot 127 time-slot 63 time-slot 31 pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 134 2001-11-16 preliminary note: the msb (pcm sign bit) must be at the beginning (first bit) of the time-slot for pcm data. for other data types (e.g. hdlc) the msb may be first or last depending on the format. the switi doesn ? t convert the data format between the pcm and h.1x0 interface. 7.4 h-bus timing figure 48 detailed data bus timing measuring conditions, data lines ? vth (threshold voltage) = 1.4 v ? vhi (test high voltage) = 2.0 v ? vlo (test low voltage) = 0.8 v ? input signal edge rate = 1 v/ns measuring conditions, clock and frame lines ? vt+ (test high voltage) = 2.0 v ? vt- (test low voltage) = 0.6 v ? input signal edge rate = 1 v/ns tfs tfp 1-bit cell tfh tc8h tc8l tc8p tdoz tzdo tdod tdiv tdv tsamp ct_frame ct_c8 data o ut data in 2.0v 0.6v 2.0v 0.6v 2.4v 0.4v 1.4v ts 0 bit 1 ts 127 bit 8 2.0v 0.8v h.100 h.110 switi_007.emf pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 135 2001-11-16 preliminary note: 1. the rise and fall times are determined by the edge rate in v/ns. a "max" edge rate is the fastest rate at which a clock transitions. 2. test load: 200 pf 3. test load: 70 pf 4. when reset is active, every output driver is tristated. 5. tc8p min and max are under free-run conditions assuming 32ppm clock accuracy. 6. non-cumulative, tc8p requirements still need to be met. 7. measured at the transmitter. 8. measured at the receiver. 9. for reference only. 10.tdoz and tzdo apply at every time-slot boundary. 11. (phase correction) results from pll timing corrections. 12.duty cycle measured at transmitter under no load conditions. 13.this range accounts for (phase correction) 14.h.110: tcell = max. clock backplane delay + max. data backplane delay + max. tzdo + (min. tdiv - max. tdv) + max. tdoz + = 26 ns + 46 ns + 11 ns + (102 ns - 83 ns) + 10 ns + 10 ns = 122 ns. max. clock delay and max. data delay are worst case numbers based on electrical simulation. 15.based on worst case electrical simulation. 16.h.110: 10%-90%. test load = 150 pf. 17.tdv = max. clock backplane delay + max. data backplane delay + max. data hiz to output time = 26 ns + 46 ns + 11 ns = 83 ns. max. clock delay and max. data delay are worst case numbers based on electrical simulation. table 29 component timing specification symbol parameter min typ max unit notes clock edge rate (all clocks except ct_netref) 0.25 2 v/ns 1 ct_netref edge rate 0.3 v/ns 16 tc8p clock ct_c8 period 122.066- 122.074+ ns 5 tc8h clock ct_c8 high time 49- 73+ ns 6, 12 tc8l clock ct_c8 low time 49- 73+ ns 6, 12 tsamp data sample point 90 ns 9 tdoz data output to hiz time - 10 0 ns 3, 7, 10 tzdo data hiz to output time 0 23 ns 3, 7, 10 tdod data output delay time 0 23 ns 3, 7 tdv data valid time 0 83 ns 8, 15,17 tdiv data invalid time 102 112 ns 13, 14 tfp ct_frame width 90 122 180 ns tfs ct_frame setup time 45 90 ns tfh ct_frame hold time 45 90 ns phase correction 0 10 ns 11 pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 136 2001-11-16 preliminary figure 49 clock skew timing note: 1. test load: 50 pf 2. assumes "a" and "b" masters in adjacent slots. 3. when static skew is 10 ns and, in the same clock cycle, each clock performs a 10 ns phase correction in opposite directions, a maximum skew of 30 ns will occur during that clock cycle. 4. meeting the skew requirements in table 30 and the clock accuracy requirements could require the plls generating ct_c8 to have different time constants when acting as primary and secondary clock masters. 5. requirements for ct_c8 and ct_frame receivers. table 30 clock skew timing symbol parameter min max unit notes tskc8 max skew between ct_c8 "a" and "b" 16 ns 1,2,3,4 tskcomp max skew between ct_c8_a and any generated compatibility clock 17 ns 1 tskout max skew between all switi output clocks 5 ns vt+ positive-going threshold 1.2 2 v 5 vt- negative-going threshold 0.6 1.6 v 5 vhys hysteresis (vt+, vt-) 0.4 v 5 cin input pin capacitance 10 pf 5 ct_c8_a ct_c8_b vt+ vt+ ct_c8_a inter-operability and pcm (local bus) clocks vt+ vt+ tskc8 tskcomp switi_080.emf pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 137 2001-11-16 preliminary 7.5 clock interoperability figure 50 sclk-d timing for scbus operating at 8.192 mbit/s note: 1. rising edge of ct_c8_ n to rising edge of sclk-d includes 5 ns of skew as with other compatibility signals ( n = current primary ct bus clock signal identifier) 2. sclk-d high and low times include nominal 3. this timing is valid under conditions specified in the pci local bus specification, rev. 2.1, table 4-2, note 4 4. ct_c8 is configured as output and sclk-d is configured as output. table 31 sclk-d timing at 8.192 mbit/s symbols parameter min. typ. max. unit tcrs rising edge of ct_c8_ n to rising edge of sclk-d 100 110 ns tsh sclk-d high time 51 61 71 ns tsl sclk-d low time 51 61 71 ns tcrs tsh tsl ct_c8 sclk-d switi_066.emf pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 138 2001-11-16 preliminary 7.6 microprocessor interface timing microprocessor accesses of the switi are performed by an activation of the address and cs . ? by driving the mode16 pin ? low ? the user selects the 8-bit microprocessor interface, by driving it ? high ? - the 16-bit microprocessor interface. ? by driving the ale pin ? high ? the user selects intel/infineon mode, by driving it ? low ? - motorola mode. the pin is sampled during the hardware reset process. ? in intel/infineon mode, a distinction is needed between working in multiplexed address/data bus mode and de-multiplexed address and data bus mode. in motorola mode, only de-multiplexed busses are used. by driving the ale pin ? high ? during the normal operation the user selects the de-multiplexed mode, a falling or rising edge during the normal operation selects the multiplexed mode. 7.6.1 infineon/intel timing in de-multiplexed mode in this mode driving rd ? low ? causes a read access, driving wr ? low ? causes a write access. in de-multiplexed bus configuration, ale must be driven ? high ? . note: the read/write recovery time (t ri and t wi ) are required only for consecutive accesses to the microprocessor interface. table 32 infineon/intel timing in de-multiplexed mode parameter symbol limit values (c load = 50pf) min max address setup time to wr or rd t as 15 ns rd pulse width t rr 60 ns rd recovery time t ri 120 ns data output delay from rd active t rd 60 ns data float delay from rd inactive t df 15 ns wr pulse width t ww 40 ns wr recovery time t wi 120 ns data setup time to wr x cs t dw 20 ns data hold time from wr x cs t wd 10 ns pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 139 2001-11-16 preliminary figure 51 infineon/intel read cycle in de-multiplexed mode figure 52 infineon/intel write cycle in de-multiplexed mode addresses will be latched with the falling wr edge during the write cycle internally. 7.6.2 infineon/intel timing in multiplexed mode in this mode the ale pin is used to lock the address send via the multiplexed a/d bus. address data t rd t rr t t ri t df t as a0-a4 rd xcs d0-d7 address data t ww t t wi t dw t t wd t as a0-a4 wr xcs d0-d7 pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 140 2001-11-16 preliminary figure 53 infineon/intel read cycle in multiplexed mode table 33 infineon/intel timing in multiplexed mode parameter symbol limit values (c load = 50pf) min max ale pulse width t aa 15 ns address setup time to ale falling edge t al 15 ns address hold time from ale falling edge t la 5ns address latch setup time to wr , rd t als 5ns rd pulse width t rr 60 ns rd recovery time t ri 120 ns data output delay from rd active t rd 60 ns data float delay from rd inactive t df 15 ns wr pulse width t ww 40 ns wr recovery time t wi 120 ns data setup time to wr x cs t dw 20 ns data hold time from wr x cs t wd 10 ns address data address t rd t rr t t la t al t ri t df t als t aa ale rd xcs ad0-ad7 pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 141 2001-11-16 preliminary figure 54 infineon/intel write cycle in multiplexed mode address data address t ww t t dw t la t al t wi t wd t t als t aa t ale wr xcs ad0-ad7 pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 142 2001-11-16 preliminary 7.6.3 motorola microprocessor timing in this mode r/w distinguishes between read and write interactions, and ds is used for timing. ds x cs is active (low) when both, ds and cs , are active (low). the ale pin must be driven ? low ? . note: ds x cs is active (low) when, both, ds and cs are active (low) table 34 motorola timing parameter symbol limit values (c load = 50pf) min max address setup time to csxds t as 15 ns r or w setup to ds t dsd 0 r/w hold from csxds inactive t rwd 0 r pulse width t rr 60 ns r recovery time t ri 120 ns data output delay from r t rd 60 ns data float delay from r t df 15 ns w pulse width t ww 40 ns w recovery time t wi 120 ns data setup time to w and cs , ds and cs t dw 10 ns data hold time from w and cs , ds and cs t wd 10 ns pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 143 2001-11-16 preliminary figure 55 motorola read cycle figure 56 motorola write cycle address data t rd t df t ri t t rr t rwd t dsd t as a0-a4 r/w csxds d0-d7 address data t wd t dw t wi t ww t t rwd t dsd t as a0-a4 r/w csxds d0-d7 pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 144 2001-11-16 preliminary 7.7 jtag interface timing table 35 jtag interface timing parameter symbol limit values unit notes min. typ. max. test clock (tck) period t tcj 100 ns test clock (tck) period low t cjl 40 ns test clock (tck) period high t cjh 40 ns tms set-up time before tck rising edge t suj 5ns tms hold time after tck rising edge t hjr 5ns tdi set-up time before tck rising edge t dse 5ns tdi hold time after tck rising edge t dhe 5ns input data set-up time t ipj 10 ns input data hold time t iaj 10 ns tdo delay after tck falling edge t odf 20 ns any output pin delay after tck falling edge t opd 25 ns in update-dr tap controller state test reset t trst 1s pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 145 2001-11-16 preliminary figure 57 boundary scan timing tck tms tdi td0 t tcj t cjl t cjh t suj t hjr t dse t dhe t odf t opd t ipj t iaj any input any output t trst trst pef 20451 / 20471 / 24471 timing diagrams preliminary data sheet 146 2001-11-16 preliminary 7.8 hardware reset timing figure 58 hardware reset timing note: in h.110 mode table 36 and figure 58 are also valid for the ct_reset signal. table 36 hardware reset timing parameter symbol limit values unit notes min. typ. max. hardware reset time t reset 1s t reset reset switi_090.emf pef 20451 / 20471 / 24471 electrical characteristics preliminary data sheet 147 2001-11-16 preliminary 8 electrical characteristics 8.1 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. table 37 absolute maximum ratings parameter symbol limit values unit ambient temperature under bias pef t a ? 40 to 85 c storage temperature t stg ? 65 to 150 c supply voltage v dd ? 0.5 to 4.6 v i/o supply voltage v dd5 ? 0.5 to 7 v voltage on any input or output pin (referenced to ground) v s ? 0.5 to v dd +0.5 ? 0.5 to v dd5 +0.5 v esd robustness 1) (hbm: 1.5 k ? , 100 pf) 1) according to mil-std 883d, method 3015.7 and esd ass. standard eos/esd-5.1-1993. v esd,hbm 1500 v pef 20451 / 20471 / 24471 electrical characteristics preliminary data sheet 148 2001-11-16 preliminary 8.2 operating range note: in the operating range, the functions given in the circuit description are fulfilled. table 38 operating range parameter symbol limit values unit min. max. operating temperature t a ? 40 85 c supply voltage v dd 3.13 3.47 v i/o supply voltage v dd5 4.75 5.25 v ground v ss 00v voltage applied to input pins 1) 1) if one of the h.1x0 input signals from the htsi are used a 5 v signal environment the special v dd5 pins must be connected to 5 v as reference voltage to fulfill the operating range. v in 05.5v voltage applied to output or i/o pins 2) outputs enabled outputs high-z 2) if one of the h.1x0 data ports and i/o signals or pcm16..31(in/out) ports from the htsi are used in a 5 v signal environment the special v dd5 pins must be connected to 5 v as reference voltage to fulfill the operating range. v out v out 0 0 v dd 5.5 v v voltage applied to h.1x0 i/o pins in 3,3v signal environment 3) outputs enabled outputs high-z 3) v dd5 are connected to 3.3 v v out v out 0 0 v dd v dd +0.3 v v pef 20451 / 20471 / 24471 electrical characteristics preliminary data sheet 149 2001-11-16 preliminary 8.3 crystal oscillator the switi requires a 16.384 mhz or 32.768 mhz clock source. to supply this a 16.384 mhz or 32.768 mhz crystal can be connected between the eclki and eclko pins. figure 59 shows a possible configuration of crystal with the external capacitors. figure 59 external crystal if a crystal is not used, a 16.384 mhz (32 ppm or less) or a 32.768 mhz (32 ppm) signal must be provided to the eclki pin and eclko should be left unconnected. table 39 external capacitances for crystal (recommendation) parameter symbol rec. values unit notes clock external input capacitance c eclki 6.8 pf clock external output capacitance c eclko 8.2 pf eclki eclko switi_061.emf 16.384 mhz 32 ppm switi pef 20451 / 20471 / 24471 electrical characteristics preliminary data sheet 150 2001-11-16 preliminary 8.4 dc characteristics note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. table 40 dc characteristics parameter symbol limit values unit notes min. max. input low voltage v il ? 0.3 0.8 v input high voltage v ih 2.0 v dd +0.3 v output low voltage v ol 0.4 v i ol =6ma i ol =24ma 1) 1) only for ct_c8, ct_frame , fr_comp , c2, c4 , c16+ , c16- , sclk, sclk-d pins output high voltage v oh 2.4 v i oh = ? 2.0 ma i oh = ? 24.0 ma 2) 2) only for ct_c8, ct_frame , fr_comp , c2, c4 , c16+ , c16- , sclk, sclk-d pins typical power supply current htsi i cc 250 ma v dd =3.3v, t a =25 c: pdc = 16.384 mhz input leakage current i il 1 a v dd =3.3v, gnd=0v; all other pins are floating; v in =0v output leakage current i oz 1 a v dd =3.3v, gnd=0v; v out =0v positive threshold v t+ 1.2 2.0 v negative threshold v t- 0.6 1.6 v hysterisis (v t+ - v t- ) v hys 0.4 v pef 20451 / 20471 / 24471 electrical characteristics preliminary data sheet 151 2001-11-16 preliminary 8.5 capacitances 8.6 ac characteristics ambient temperature under bias range, vdd = 3.3 v 5 %. inputs are driven to 2.4 v for a logical ? 1 ? and to 0.4 v for a logical ? 0 ? . timing measurements for the h.1x0 clock and frame lines are made at 2.0 v for a logical ? 1 ? and at 0.6 v for a logical ? 0 ? . timing measurements for all other signals are made at 2.0 v for a logical ? 1 ? and at 0.8 v for a logical ? 0 ? . the ac-testing input/output wave forms are shown below. figure 60 i/o wave form for ac-test table 41 input/output capacitances parameter symbol limit values unit notes typ. eclki input capacitance c eclki 7pf f c =1 mhz the pins, which are not under test, are connected to gnd eclko output capacitance c eclko 7pf input capacitance c in 5pf output capacitance c out 5pf test points 2.4 v 0.4 v 2.0 v 0.8 v 0,6 v 2.0 v d evice u nder t est cl = 50 pf (pcm 150 pf h.1x0 12 pf) 0.8 v 0,6 v pef 20451 / 20471 / 24471 package outlines preliminary data sheet 152 2001-11-16 preliminary 9 package outlines figure 61 outlines of p-bga-217-1 p-bga-217-1 (plastic ball grid array package) sorts of packing package outlines for tubes, trays etc. are contained in our data book ? package information ? . dimensions in mm smd = surface mounted device pef 20451 / 20471 / 24471 preliminary data sheet 153 2001-11-16 preliminary a analog pll 32 analyze memory 30 b bidirectional switching 26 boundary scan 54, 56 broadcast 7 broadcast switching 26 c clock fallback 37, 39 clock shift 6 constant delay 6, 25 d data rate adaption 7 e error handling - switching 30 f fallback - primary master 39 fallback - secondary master 40 fallback - slave 41 flexible data rates 6 frame group 53 framing group 8 g general purpose clocks 8, 53 gpio port 8, 52 i initialization procedure 107 input/output tolerance 8 interrupt handling 97 interrupts masking 98 l local bus interface 19, 44 pef 20451 / 20471 / 24471 preliminary data sheet 154 2001-11-16 preliminary m master - slave combination pcm/h.1x0 36 message mode 7 microprocessor interface 8, 21, 24, 50 minimum delay 6 multipoint 7 multipoint switching 25 p parallel mode 4, 7, 29, 131 phase alignment 35 r read access 7, 96 register configuration command register 1 68 configuration command register 2 74 configuration register 89 connection command register 66, 92 destination address register 91 destination port address register 62 general input register 92 general input register 1 63 general input register 2 65 general purpose direction register 84 general purpose interrupt register 85 general purpose mask register 84 general purpose port input register 83 general purpose port output register 84 idcode register 94 input time slot address register 61 interrupt error mask register 1 82 interrupt error mask register 2 83 interrupt error status register 93 interrupt error status register 1 79 interrupt error status register 2 80 interrupt mask register 1 81 interrupt status register 1 78 message value register 78 output time slot address register 62 source address register 91 source port address register 61 pef 20451 / 20471 / 24471 preliminary data sheet 155 2001-11-16 preliminary sub-channel address register 62 time slot value / configuration register 94 time slot value register 85 s stream-to-stream switching 7, 27 sub-channel switching 6, 117 switching factory 25 w write access 7, 96 http://www.infineon.com published by infineon technologies ag infineon goes for business excellence ? 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